Dielectric CMP Stop Layer for Backside Power Network Integration
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Solution Overview
Problem
The miniaturization of semiconductor devices poses challenges in forming efficient power delivery networks, leading to routing congestion and structural instability due to the difficulty in separately forming signal and power patterns on the same wiring layer, which affects the integration and performance of semiconductor devices.
Innovation Solution
A method for manufacturing semiconductor devices involving the formation of a doped dielectric film with a lower polishing rate than the first and second dielectric films, using chemical mechanical polishing (CMP), which enhances structural stability and allows for the separation of power and signal patterns, enabling improved routing and integration by forming a back-side power delivery network (BSPDN) structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a planarization process such as CMP is used for wide-area planarization, then manufacturing precision is improved, but structural stability deteriorates due to over-polishing and bonding defects
Solution Approach 1:
The patent applies local quality by forming a doped dielectric film with different material properties (lower polishing rate) at specific locations (between wiring structures) compared to the surrounding undoped dielectric films. This localized modification allows the central region to resist over-polishing while maintaining planarization precision in other areas, thereby preventing bonding defects and structural bending.
2Productivity
If signal and power patterns are formed on the same wiring layer, then device integration is improved, but routing congestion increases causing structural instability
Solution Approach 1:
The patent resolves routing congestion by transitioning from a two-dimensional planar wiring layout to a three-dimensional structure with multiple wiring layers. Power patterns and signal patterns are separated onto different layers, with the doped dielectric film providing structural support between layers. This vertical dimensionality change enables high integration without routing congestion on any single layer.
3Stability of the object's composition
If the polishing rate of the doped dielectric film is reduced, then structural stability is improved by preventing over-polishing, but manufacturing precision deteriorates due to difficulty in controlling polishing depth
Solution Approach 1:
The doped dielectric film acts as an intermediary layer with distinct material properties between the upper and lower undoped dielectric films. During CMP, this intermediate layer polishes at a different rate, creating a controlled depth differential that prevents over-polishing of the central region while maintaining overall planarization precision through the layered structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves structural stability and routability by reducing the polishing rate of the doped dielectric film, preventing bonding defects and structural bending, thus enhancing the integration and performance of semiconductor devices.
Implementation Method 1
polishing the second dielectric film by a chemical mechanical polishing (CMP) method
Implementation Method 2
doping a surface of the first dielectric film with impurities to form a doped dielectric film
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first dielectric film on a front-side surface of a substrate that has the front-side surface and a back-side surface, doping a surface of the first dielectric film with impurities to form a doped dielectric film covering at least a portion of the first dielectric film, forming a second dielectric film on the doped dielectric film, and polishing the second dielectric film by a chemical mechanical polishing (CMP) method. The doped dielectric film has a polishing rate less than a polishing rate of each of the first dielectric film and the second dielectric film.