Dielectric Collar Formation for Uneven-Height Semiconductor Wires
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Solution Overview
Problem
Existing methods for forming dielectric collars around semiconductor wires with varying heights are ineffective, leading to inconsistent collar formation and reduced yield in semiconductor-based LED devices, as they fail to properly protect the lower parts of the wires with better crystal quality, causing leakage current issues.
Innovation Solution
A method involving the formation of a base layer and a capping layer using dielectric material, where the base layer spreads parallel to the basal plane and the capping layer surrounds the upper part of the semiconductor wires, followed by anisotropic etching to remove the dielectric material from the top part while preserving it at the lower part, ensuring each dielectric collar is adjusted to the individual wire's height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conformal dielectric layer is deposited and isotropic etching is performed to form a dielectric collar, then the collar formation process is simple and follows standard manufacturing steps, but the method fails to produce effective collars for semiconductor wires with different heights
Solution Approach 1:
The dielectric layer is segmented into two distinct parts: a base layer at the lower part of the semiconductor wire and a capping layer at the upper part. This segmentation allows each layer to serve different functions - the base layer forms the collar while the capping layer protects the upper wire during etching, enabling effective collar formation for wires of varying heights
Solution Approach 2:
The invention transitions from a single uniform dielectric layer to a two-layer structure with different thicknesses and positions. By adding the vertical dimension of layer differentiation, the process can accommodate wires of different heights while maintaining effective collar formation
2Device complexity
If the dielectric collar is formed using the conventional method, then the process steps are few and straightforward, but the leakage current at the lower part of semiconductor wires is not effectively minimized
Solution Approach 1:
The dielectric material is applied with local quality differentiation - the base layer at the lower part has sufficient thickness to effectively minimize leakage current, while the capping layer at the upper part has different thickness characteristics. This localized optimization ensures reliable leakage current reduction without unnecessarily complicating the overall process
3Manufacturing precision
If spin coating is used to form the base and capping layers, then the dielectric material can be precisely deposited at different heights, but the process requires additional manufacturing steps
Solution Approach 1:
The spin coating process parameters (rotation speed, time, material viscosity) are changed to create a thickness gradient across the dielectric layer. By modifying these parameters, the base layer and capping layer are formed with different thicknesses in a controlled manner, achieving precise thickness control while using a single deposition step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms dielectric collars that are proportional to the height of each semiconductor wire, protecting the lower parts with better crystal quality and preventing leakage current, thereby improving the efficiency and yield of semiconductor-based LED devices.
Implementation Method 1
forming, at least partially by spin coating, a base layer at a lower part of the SW, and possibly a capping layer at an upper part of the SW
Implementation Method 2
Performing an anisotropic etching along the direction normal to the basal plane so as to remove the dielectric material at least at a top part of the upper part of the SW
Data Source
AI summary
A method of forming a dielectric collar for semiconductor wires includes providing a layers stack and a semiconductor wires (SW) layer on top of the stack, forming a base layer at a lower part of the SW and a capping layer at an upper part of the SW, the base layer parallel to the basal plane and including a dielectric material surrounding the lower part of the SW, and the capping layer along a contour of the SW and including a dielectric material surrounding the upper part of the SW, the base and capping layers having thicknesses e1 and e2 with e1>2.e2, performing anisotropic etching along the direction normal to the basal plane to remove the dielectric material at a top part of the SW and leaving the dielectric material at least in the lower part of the SW.