Dielectric Layer Deposition for Passive Device Dimension Control

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Solution Overview

Problem

Existing semiconductor technologies face challenges in accurately controlling the dimensions of passive devices like resistors, leading to performance variations and reliability issues, especially in advanced technology nodes with smaller feature sizes, resulting in defects such as leakage and short circuits.

Innovation Solution

A semiconductor structure and method where a dielectric material layer is deposited in contact holes to form a capacitor or resistor, allowing precise control of resistance or capacitance through thickness control, and is compatible with advanced technology nodes like the 7 nm node, reducing manufacturing complexity and improving device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If etching is used to form passive devices like resistors, then the fabrication process can be implemented, but the dimension control is inaccurate leading to high device parameter variations

Engineering Contradiction:

Improvedimension control of passive deviceVSAvoiddevice parameter consistency

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent replaces the mechanical etching process with a deposition process to form the dielectric material layer for passive devices. Instead of removing material through etching, the dielectric layer is deposited to a controlled thickness to define the resistance value, enabling precise dimensional control and consistent device parameters.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The invention changes the controlling parameter from etch depth (which is difficult to control precisely) to film thickness (which can be controlled with atomic layer precision through deposition). The resistance value is determined by the thickness of the dielectric material layer, allowing accurate control of passive device dimensions.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If existing semiconductor technologies are used in advanced technology nodes with smaller feature sizes, then device integration is achieved, but misalignments cause leakage, short, opening or other failure defects

Engineering Contradiction:

Improvedevice integration capabilityVSAvoiddefect rate in advanced nodes

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The deposited dielectric material layer automatically conforms to the underlying topography and self-aligns with contact holes and active regions. The deposition process inherently provides better alignment than etching, reducing misalignment-induced defects such as leakage and shorts in advanced technology nodes.

Inventive Principle:

Principle #25Self-service

3Ease of manufacture

If etching is used to form passive devices, then the fabrication can proceed, but the process has limited and inaccurate control leading to high processing variation

Engineering Contradiction:

Improvefabrication process implementabilityVSAvoidcontrol accuracy of passive device dimensions

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent substitutes the etching mechanism with a deposition mechanism. The dielectric material layer is formed by depositing material onto the substrate, which provides superior thickness control compared to etching depth control. This enables accurate dimensional control while maintaining ease of manufacture through standard deposition equipment.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enables precise control of device parameters, enhancing reliability and compatibility with advanced technology nodes by using deposition to form the dielectric material layer, thereby reducing defects and improving performance consistency.

Implementation Method 1

a dielectric material layer is deposited in contact holes to form a capacitor or resistor, allowing precise control of resistance or capacitance through thickness control

Methodology Applied

Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11152355B2Structure with embedded memory device and contact isolation scheme

Publication Date: 2021.10.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.