Middle-of-Line Dielectric Engineering for Via Void Reduction
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Solution Overview
Problem
Conventional interconnect formation processes in semiconductor devices result in high resistance structures due to the use of materials like titanium nitride and tantalum nitride, which hinder the development of next-generation VLSI and ULSI devices with shrinking dimensions, leading to increased manufacturing costs, power consumption, and reduced chip performance.
Innovation Solution
A method involving the formation of a dielectric layer with openings filled with metal, followed by implanting an oxygen-containing species to promote oxidation and create a metal oxide layer, reducing interconnect resistance by closing gaps between the metal and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal barrier and liner layers (such as TiN or TaN) are used for via fill, then reliability and gap-fill robustness are improved, but interconnect resistance increases due to high material resistivity
Solution Approach 1:
The patent removes the conventional metal barrier and liner layers (TiN, TaN) from the via fill structure, extracting the problematic high-resistivity materials that cause RC delay and power loss. This extraction eliminates the source of high interconnect resistance while maintaining gap-fill robustness through alternative means.
Solution Approach 2:
The patent changes the material parameter by replacing high-resistivity metal nitrides with low-resistivity materials such as tungsten or copper. This parameter change directly reduces interconnect resistance and associated energy loss while maintaining the structural integrity and reliability of the interconnect formation process.
2Manufacturing precision
If via dimension is reduced below 40 nm to increase circuit density, then manufacturing precision is improved, but interconnect resistance increases due to higher resistance through smaller via dimensions
Solution Approach 1:
The patent changes the material parameter by using low-resistivity fill materials (tungsten, copper) that compensate for the increased resistance effect of smaller via dimensions. This allows continued scaling below 40 nm while controlling interconnect resistance through superior material conductivity rather than larger dimensions.
Solution Approach 2:
The patent employs composite material strategies by combining low-resistivity metals with appropriate dielectric materials, creating an optimized interconnect structure that maintains low resistance even at reduced via dimensions. The composite structure addresses both the dimensional scaling requirements and the electrical performance requirements.
3Device complexity
If multiple layer routings with via stacks are implemented to increase interconnect density, then circuit complexity is improved, but interconnect resistance increases due to cumulative resistance through multiple via stacks
Solution Approach 1:
The patent changes the material parameter by using low-resistivity materials that reduce the resistance contribution of each individual via in the stack. This allows multiple via stacks to be used for achieving interconnect density and routing complexity while the cumulative resistance remains controlled due to the superior conductivity of the fill materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces interconnect resistance, enhancing chip performance, decreasing manufacturing costs, and improving the density and quality of semiconductor devices by forming reliable, low-resistance interconnects.
Implementation Method 1
implanting an oxygen containing species into the dielectric layer to provide a dose of the oxygen containing species to the surface of each of the one or more openings and the metal disposed thereon
Data Source
AI summary
Embodiments of the present disclosure provide techniques for fabricating a semiconductor device with fewer via voids (e.g., gaps between a dielectric layer and a metal fill of the semiconductor device). One such technique involves forming a dielectric layer over a surface of a substrate, forming one or more openings in the dielectric layer, filling the one or more openings with a metal wherein the metal is disposed on a surface of each of the one or more openings, and implanting an oxygen containing species into the dielectric layer to provide a dose of the oxygen containing species to the surface of each of the one or more openings and the metal disposed thereon.