Dielectric Etch Stop Layer for Buried Digit Line Shorts
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Solution Overview
Problem
The fabrication of buried digit lines in semiconductor memory devices requires multiple masking layers, increasing manufacturing time and cost due to the need for precise alignment and protection against over-etching and misaligned pattern etching, which can lead to shorts and contact resistance issues.
Innovation Solution
The use of a dielectric etch stop layer, such as aluminum oxide or silicon carbide, reduces the number of masking layers needed by preventing over-etching and misaligned etching, thereby protecting the structures and maintaining electrical properties while allowing for fewer process steps and lower fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking layers are used to fabricate buried digit lines, then alignment precision and protection against over-etching are improved, but manufacturing time and cost increase
Solution Approach 1:
The patent extracts the etch-stop function from the masking layers and assigns it to a dedicated etch stop layer. This separation allows the masking layers to focus solely on pattern definition while the etch stop layer independently prevents over-etching, enabling fewer masking layers to be used without sacrificing protection functionality.
Solution Approach 2:
The etch stop layer acts as an intermediary between the masking layers and the underlying structures. It provides a controlled etching barrier that prevents direct exposure of sensitive structures, thereby maintaining protection functionality while reducing the number of masking layers required.
2Reliability
If multiple masking layers are used to fabricate buried digit lines, then protection against over-etching and misaligned pattern etching is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts the etch-stop function from the masking layers and assigns it to a dedicated etch stop layer. This separation allows the masking layers to focus solely on pattern definition while the etch stop layer independently prevents over-etching, enabling fewer masking layers to be used without sacrificing protection functionality.
Solution Approach 2:
The etch stop layer serves as a sacrificial or temporary structure that performs its protective function during etching and can be subsequently removed or integrated into the final structure. This disposable approach provides reliable protection at lower cost compared to using multiple expensive masking layers.
3Area of stationary object
If critical dimensions are reduced to increase density, then area is reduced, but contact resistance increases due to smaller contact size
Solution Approach 1:
The patent performs preliminary etching through the etch stop layer to create enlarged contact openings before depositing the buried digit line. This preliminary action ensures that the contact area is sufficiently large to maintain low contact resistance, even when the overall critical dimensions are reduced for increased density.
Data Source
AI summary
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS gates, NMOS gates, memory cells, P+ active areas, and N+ active areas. These structures are fabricated through the use of multiple masking processes, which may cause shorts when a buried digit layer is deposited if the masking processes are misaligned. Accordingly, a dielectric etch stop layer, such as aluminum oxide Al2O3 or silicon carbide SiC, may be utilized in the array to prevent shorts between the wordlines, active areas, and the buried digit layer when the contacts are misaligned.