Dielectric Etch-Stop for Source Drain Isolation

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Solution Overview

Problem

In semiconductor device fabrication, particularly for nanosheet FETs and FinFETs, the integration of source and drain regions with the substrate leads to parasitic leakage, degrading performance due to epitaxy contacting the substrate and the high-k metal gate stack, necessitating improved isolation methods without additional masks or limited canyon space designs.

Innovation Solution

A method involving the formation of a full bottom dielectric isolation layer using a sacrificial bottom isolation layer that is selectively etched without removing the channel or sacrificial layers, creating air gaps between the source/drain regions and the substrate, and using self-aligned dielectric etch stops to prevent over-etching, thereby isolating the nanosheet or Fin regions from the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If source and drain regions are integrated with the substrate, then device density is improved, but parasitic leakage increases degrading performance

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the substrate into isolated regions by introducing air gaps between source/drain regions and the substrate. This segmentation prevents continuous parasitic current paths while maintaining high device density through the nanosheet architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary air gap structure between the source/drain regions and the substrate. This air gap acts as a mediator that electrically isolates the regions, blocking parasitic leakage paths while allowing the device density to remain high.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If additional masks are used for isolation, then parasitic leakage is reduced, but device complexity and manufacturing steps increase

Engineering Contradiction:
Improveparasitic leakageVSAvoidmanufacturing steps
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The isolation structure is formed preliminarily during the nanosheet fabrication process itself, rather than requiring additional post-fabrication masks. The air gap isolation is created as part of the nanosheet release process, integrating multiple functions into existing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The nanosheet fabrication process serves multiple functions: it creates the channel structure, releases the nanosheets from the substrate, and simultaneously forms the air gap isolation structures. This multi-functionality eliminates the need for separate isolation masks and steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If substrate over-etching occurs during spacer/fin etching, then manufacturing precision is compromised, but etching completeness is improved

Engineering Contradiction:
Improveetch controlVSAvoidetching completeness
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The etch process is designed to be self-limiting, where the air gap structure itself serves as an etch stop. When the etch reaches the air gap, it naturally stops without requiring external control mechanisms, preventing substrate over-etching while ensuring complete spacer/fin removal.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The air gap structure is prepared beforehand as a protective cushion during etching. This pre-formed gap acts as a buffer that stops the etch process before it can damage the substrate, ensuring manufacturing precision is maintained.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively isolates source and drain regions from the substrate, reducing parasitic leakage and enhancing device performance by providing silicon-on-insulator-like isolation without requiring additional masks or limited canyon space designs, while preventing substrate over-etching during spacer/fin etching operations.

Implementation Method 1

removing at least a portion of the bottom sacrificial layer so as to create openings

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

forming an isolation layer on the inner spacers so as to form an air gap

Methodology Applied
Scientific EffectDielectric deposition:

Data Source

PatentUS10741639B2Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection
Publication Date: 2020.08.11 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10741639B2 patent drawing
  • US10741639B2 patent drawing
  • US10741639B2 patent drawing

AI summary

A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.