Dielectric Etch Stop Layer Formation for Closely Spaced Semiconductor Lines
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Solution Overview
Problem
The existing deposition techniques for forming dielectric interlayers in semiconductor devices with densely spaced lines, such as polysilicon lines and gate electrodes, face challenges in achieving reliable gap filling and void-free deposition, especially as feature sizes shrink below 100 nm, leading to reliability concerns and complex CMP processes.
Innovation Solution
The technique involves reducing the size of sidewall spacers before depositing the etch stop layer, using a plasma etch process to increase the spacing between lines, and employing enhanced gap-filling deposition techniques like sub-atmospheric CVD or high-density plasma CVD to form a void-free etch stop and interlayer dielectric, allowing for further device scaling without laborious process adaptations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If well-established PECVD techniques are used for high-rate deposition of silicon nitride and silicon dioxide, then deposition efficiency is improved, but gap-fill capabilities become insufficient for closely spaced lines with spacing of 100 nm or less
Solution Approach 1:
The patent applies preliminary action by reducing the spacer elements before depositing the etch stop layer. This pre-processing step increases the effective spacing between lines, allowing subsequent high-rate PECVD deposition to successfully fill the gaps without void formation. The spacer reduction is performed using a plasma etch process with selective removal of spacer material.
Solution Approach 2:
The patent changes the physical parameters of the deposition process by using sub-atmospheric CVD or high-density plasma CVD instead of standard PECVD. These parameter changes enable enhanced gap-fill capabilities while maintaining acceptable deposition rates, allowing reliable formation of etch stop layers and interlayer dielectrics over closely spaced lines.
2Reliability
If spacer elements are reduced to increase spacing between lines, then deposition reliability is improved, but additional process steps are required
Solution Approach 1:
The patent applies universality by using a plasma etch process that serves multiple functions: it reduces the spacer elements to increase spacing, and simultaneously prepares the surface for subsequent deposition. This multi-functional approach increases deposition reliability while minimizing the addition of separate process steps.
3Area of moving object
If feature sizes are scaled down to increase circuit density, then device capacity is improved, but spacing between lines decreases to 100 nm or less causing deposition failures
Solution Approach 1:
The patent applies preliminary action by reducing the spacer elements before depositing the etch stop layer. This pre-processing step increases the effective spacing between lines, allowing subsequent high-rate PECVD deposition to successfully fill the gaps without void formation. The spacer reduction is performed using a plasma etch process with selective removal of spacer material.
Solution Approach 2:
The patent changes the physical parameters of the deposition process by using sub-atmospheric CVD or high-density plasma CVD instead of standard PECVD. These parameter changes enable enhanced gap-fill capabilities while maintaining acceptable deposition rates, allowing reliable formation of etch stop layers and interlayer dielectrics over closely spaced lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable, void-free deposition of etch stop and interlayer dielectrics, enhancing the reliability of semiconductor devices and reducing production complexity by maintaining well-established deposition and CMP processes, even at advanced technology nodes like 90 nm.
Implementation Method 1
material is removed from the first and second spacer elements to increase the spacing by means of a selective etch process
Implementation Method 2
an etch stop layer is deposited above the structure
Implementation Method 3
employing enhanced gap-filling deposition techniques like sub-atmospheric CVD
Implementation Method 4
employing enhanced gap-filling deposition techniques like sub-atmospheric CVD or high-density plasma CVD
Data Source
AI summary
When forming line structures of semiconductor devices in accordance with the 90 nm technology, sidewall spacers of the lines are reduced in size immediately prior to the deposition of an etch stop layer that is formed on the device layer. Due to the reduced spacer elements or due to a complete removal of the spacer elements, the subsequent deposition of the etch stop layer and of the interlayer dielectric is significantly enhanced with respect to void formation and defect rate.