Dielectric Etch Stop Layer for 3D Memory Plug Defect Reduction
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Solution Overview
Problem
In 3D memory devices, semiconductor plugs formed through selective epitaxial growth often suffer from defects due to nitrogen accumulation and uneven growth, leading to reliability and yield issues, as well as substrate damage during etching processes.
Innovation Solution
A dielectric etch stop layer, made from high-dielectric constant materials or native oxide, is introduced to prevent nitrogen accumulation and substrate damage, allowing for uniform semiconductor plug growth by stopping etching processes and maintaining the substrate's integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If selective epitaxial growth is used to form semiconductor plugs, then the plugs can be formed with controlled dimensions, but nitrogen accumulation and uneven growth occur leading to defects
Solution Approach 1:
A dielectric layer is formed on the substrate before the selective epitaxial growth process. This preliminary layer prevents nitrogen accumulation and substrate damage during the growth process, ensuring uniform plug formation without defects while maintaining dimensional control.
Solution Approach 2:
The dielectric layer acts as an intermediary between the substrate and the semiconductor plug. It mediates the interaction by preventing direct contact between the substrate and etching chemicals, thereby preventing nitrogen accumulation and substrate damage while allowing controlled plug growth.
2Ease of manufacture
If etching processes are used to form openings, then the dielectric stack can be penetrated, but substrate damage occurs
Solution Approach 1:
The dielectric layer serves as a protective intermediary that stops the etching process before it reaches the substrate. This allows openings to be formed through the dielectric stack while preventing substrate damage, maintaining both manufacturability and substrate integrity.
Solution Approach 2:
The dielectric layer is placed beforehand to cushion and protect the substrate from the harmful effects of the etching process. It absorbs the etching action, preventing direct damage to the substrate while still allowing the openings to be formed as needed.
3Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar memory cell scaling to three-dimensional vertical channel structures. By growing semiconductor plugs vertically through selective epitaxial growth and forming vertical channels, the design moves to another dimension, achieving higher memory density without the prohibitive complexity of further planar scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dielectric etch stop layer significantly reduces defects in semiconductor plugs, enhancing the reliability and yield of 3D memory devices by ensuring uniform growth and preventing substrate damage, thus improving the electrical performance and structural integrity of the devices.
Implementation Method 1
A dielectric etch stop layer is introduced to prevent nitrogen accumulation and substrate damage, allowing for uniform semiconductor plug growth by stopping etching processes and maintaining the substrate's integrity
Implementation Method 2
forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate
Data Source
AI summary
Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening. The method further includes forming a memory stack comprising a plurality of interleaved dielectric layers and conductor layers by replacing the sacrificial layers in the dielectric stack with the conductor layers.