Dielectric Fin Anti-Fuse Memory Cells for High-Density PUFs
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Solution Overview
Problem
Existing anti-fuse memory devices face challenges in integrating high-density PUF signatures due to manufacturing variability and reverse-engineering concerns, requiring innovative solutions for secure authentication and efficient programming.
Innovation Solution
The implementation of anti-fuse memory cells with a pair of programming transistors and multiple pairs of reading transistors, where the programming transistors are formed with a gate-all-around configuration and isolated by a dielectric fin structure, allowing for random breakdown and generation of unique PUF signatures, improving reading performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse memory cells are used for high-density PUF signatures, then secure authentication and manufacturing variability are addressed, but device complexity and reverse-engineering concerns increase
Solution Approach 1:
The memory cell is segmented into multiple specialized transistor pairs (programming transistors and reading transistors) with distinct functions. The programming transistors are isolated by dielectric fin structures, creating independent breakdown regions that generate unique PUF signatures while maintaining secure authentication capabilities
Solution Approach 2:
Dielectric fin structures serve as intermediary elements that isolate the programming transistors from each other. This isolation prevents reverse-engineering attacks by ensuring that breakdown events in one transistor do not affect adjacent transistors, while still allowing the system to function as an integrated memory cell
2Reliability
If programming transistors are isolated by dielectric fin structures, then reading performance and power consumption are improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric fin structures provide localized isolation specifically where programming transistors are positioned, rather than requiring uniform isolation across the entire device. This localized approach improves reading performance by preventing interference between adjacent programming regions while reducing the overall manufacturing precision burden compared to complete uniform isolation
3Reliability
If gate-all-around configuration is used for programming transistors, then unique PUF signatures are generated, but area occupied by memory cell increases
Solution Approach 1:
The gate-all-around configuration wraps the gate structure completely around the channel region, transitioning from a planar 2D gate configuration to a 3D surrounding configuration. This dimensional change enables unique PUF signature generation through consistent breakdown characteristics while improving space utilization efficiency compared to traditional planar gates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the generation of unique PUF signatures for secure authentication, enhances reading performance, and reduces power consumption while allowing for high-density integration of anti-fuse memory cells, addressing reverse-engineering concerns and manufacturing variability.
Implementation Method 1
a dielectric fin structure interposed between the gate structures
Implementation Method 2
programming transistors are formed with a gate-all-around configuration
Implementation Method 3
The anti-fuse memories include a number of anti-fuse memory cells (or bit cells), whose terminals are disconnected before programming, and are shorted (e.g., connected) after the programming. The gate dielectric of the programming MOS transistor may be broken down to cause the gate and the source or drain of the programming MOS transistor to be interconnected.
Data Source
AI summary
A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.