Dielectric Fin Layout for FinFET Dummy Gate Gap Control
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently forming fin field-effect transistors (FinFETs) with high integration density and reliability due to limitations in the deposition and removal of dummy gate structures, which affect the gap regions between semiconductor and dielectric fins, impacting the deposition yield and subsequent processing steps.
Innovation Solution
The process involves forming a silicon layer over both semiconductor and dielectric fins, followed by a dummy dielectric layer, which is then removed from the dielectric fin to widen the gap region, allowing for improved deposition and removal of the dummy gate, and subsequent adjustments to dimensions and process parameters to enhance fabrication efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If narrow gap regions are present between semiconductor and dielectric fins, then integration density is improved, but deposition and removal of dummy gates becomes difficult
Solution Approach 1:
The gap region is segmented into multiple sections by introducing dielectric fins that divide the continuous gap into discrete segments. This segmentation allows dummy gates to be deposited and removed in manageable portions, solving the difficulty of handling narrow gap regions while maintaining high integration density.
Solution Approach 2:
Dielectric fins are introduced as intermediary structures between the semiconductor fins. These intermediary dielectric fins create controlled gaps that facilitate the deposition and removal of dummy gates, acting as mediators that enable the manufacturing process while preserving the high-density integration.
2Quantity of substance
If integration density is increased, then more components are integrated into given area, but fabrication efficiency and yield decrease
Solution Approach 1:
Dielectric fins are formed in advance before the dummy gate deposition and removal processes. This preliminary action prepares the structure with pre-defined gap regions, making subsequent dummy gate operations easier and more reliable, thereby improving fabrication efficiency and yield while maintaining high integration density.
Solution Approach 2:
The physical parameters of the gap regions are changed by introducing dielectric fins, which modify the gap dimensions and distribution. This parameter change creates optimal conditions for dummy gate deposition and removal, resolving the conflict between high integration density and fabrication efficiency.
3Ease of manufacture
If gap regions are widened to facilitate dummy gate operations, then ease of manufacture improves, but integration density decreases
Solution Approach 1:
The gap regions are modified locally by introducing dielectric fins at specific positions, rather than uniformly widening all gaps. This local quality change creates favorable conditions for dummy gate operations in critical areas while maintaining tight spacing in other areas, thus preserving overall integration density.
Solution Approach 2:
Instead of widening gaps in the horizontal plane, the solution introduces a vertical dimension by stacking dielectric fins between semiconductor fins. This dimensional change creates additional space for dummy gate operations without reducing the horizontal integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of FinFETs with increased efficiency, improved yield, and better performance and reliability by widening the gap regions for better dummy gate deposition and removal, facilitating more precise control over feature dimensions and process parameters.
Implementation Method 1
depositing a silicon layer over a first surface of the first semiconductor fin, a second surface of the dielectric fin, and a third surface of the isolation region; removing a portion of the oxide layer and the silicon layer to expose the second surface of the dielectric fin
Implementation Method 2
forming an oxide layer over the silicon layer
Implementation Method 3
removing a portion of the oxide layer and the silicon layer to expose the second surface of the dielectric fin
Data Source
AI summary
In an embodiment, a method includes: forming a plurality of fins over a substrate, the plurality of fins comprising: a first semiconductor fin adjacent to an isolation region; and a dielectric fin embedded in the isolation region; depositing a silicon layer over a first surface of the first semiconductor fin, a second surface of the dielectric fin, and a third surface of the isolation region; forming an oxide layer over the silicon layer; removing a portion of the oxide layer and the silicon layer to expose the second surface of the dielectric fin; forming a dummy gate over a remaining portion of the oxide layer and between the plurality of fins; forming a first epitaxial region in the first semiconductor fin; and replacing the dummy gate with a gate structure.