Dielectric Fin GAA Memory Cells for Lower Gate Leakage
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Solution Overview
Problem
Existing anti-fuse memory technologies face challenges with increased gate leakage and real estate occupancy due to shared programming transistors, which affect performance and integration in advanced technologies.
Innovation Solution
The implementation of nanostructure transistors with gate-all-around configurations and isolated gate structures using a dielectric fin structure to eliminate leakage paths and reduce memory cell size, allowing for more efficient programming and reading operations while minimizing real estate usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared programming transistors are used in anti-fuse memory cells, then device complexity is reduced, but gate leakage increases and performance deteriorates
Solution Approach 1:
The patent divides the programming function into separate dedicated programming transistors for each memory cell or column, eliminating the shared transistor architecture. This segmentation removes the leakage paths that occurred when multiple cells shared a common programming transistor, thereby reducing gate leakage while maintaining manageable device complexity through systematic organization.
Solution Approach 2:
The patent extracts the programming function from shared transistors and assigns it to dedicated programming transistors. By taking out the programming function from the shared architecture and giving it to dedicated structures, the harmful leakage effects are eliminated while preserving the essential programming capability of the anti-fuse memory cells.
2Productivity
If more memory cells are integrated in a given area, then productivity increases, but real estate occupancy per cell increases due to larger transistor structures
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional gate-all-around nanostructure transistors. By wrapping the gate structure around the channel in multiple dimensions, the transistor achieves better control and higher density without proportionally increasing the planar footprint, enabling more memory cells to be integrated in a given area.
Solution Approach 2:
The gate structure is nested around the channel structure in a gate-all-around configuration, with the gate wrapping completely around the channel. This nested arrangement maximizes the control gate has over the channel while minimizing the lateral space required, thereby reducing the area occupied by each transistor and increasing overall integration density.
3Reliability
If gate-all-around nanostructure transistors are implemented, then manufacturing precision requirements increase, but device performance and lifetime are enhanced
Solution Approach 1:
The patent employs preliminary patterning and sacrificial layer formation before creating the final gate-all-around structure. By preparing the structure in advance with sacrificial materials and pre-formed patterns, the complex nanostructure fabrication is broken down into manageable steps that can be executed with standard manufacturing processes, reducing the overall precision requirements.
Solution Approach 2:
The patent uses sacrificial layers and intermediary structures during fabrication that are later removed or transformed into the final structure. These intermediary elements serve as placeholders and guides that simplify the manufacturing process, allowing the complex gate-all-around nanostructures to be formed with less stringent precision requirements by using self-aligned processes.
Data Source
AI summary
A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.