Dielectric Fin Gate Structure for Short-Channel FinFET Control
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Solution Overview
Problem
The scaling down of transistor gate lengths leads to short-channel effects such as Drain-Induced Barrier Lowering (DIBL) and degradation of sub-threshold slope, compromising current control and transistor performance.
Innovation Solution
The formation of integrated circuit structures with tapered and rounded top dielectric fin structures improves the windows for depositing gate structures, enhancing the control of current flow and reducing short-channel effects by allowing for a larger window for gate deposition and maintaining manufacturing simplicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate length is scaled down to increase drive current, then transistor performance is improved, but short-channel effects (DIBL and sub-threshold slope degradation) worsen
Solution Approach 1:
The patent introduces a three-dimensional FinFET structure with vertical fins extending from the substrate, transforming the traditional planar two-dimensional channel into a three-dimensional structure. This dimensional change provides additional gate control surfaces (top and sidewalls) that effectively suppress short-channel effects while maintaining scaled gate lengths for high drive current
Solution Approach 2:
The channel region is segmented into multiple vertical fins rather than a single planar channel. Each fin acts as an independent current path with its own gate control, allowing the gate to exert stronger control over the total current flow. The segmented fin structure increases the effective channel width while maintaining control authority
2Ease of manufacture
If conventional planar structures are used, then manufacturing is simple, but gate deposition window is insufficient for effective control
Solution Approach 1:
Dielectric fin structures are formed in advance before gate deposition, creating pre-defined geometric features with tapered and rounded tops. These preliminary structures establish optimal gate deposition windows and provide precise alignment references, enabling effective gate control without complicating the overall manufacturing process
Solution Approach 2:
The dielectric fin structures feature rounded tops instead of sharp edges, creating smooth curved surfaces that improve gate material deposition uniformity. The curvature eliminates sharp corners that would cause deposition defects, while the tapered shape provides gradual transitions that enhance gate control and reduce stress concentrations
Data Source
AI summary
A device includes a semiconductor fin, an isolation layer, a dielectric fin structure, and a gate structure. The semiconductor fin is over a substrate. The isolation layer is over the substrate and adjacent the semiconductor fin. The dielectric fin structure is over the isolation layer and includes a bottom dielectric fin and a top dielectric fin. The isolation layer surrounds a bottom of the bottom dielectric fin. The top dielectric fin is over the bottom dielectric fin and is spaced apart from the isolation layer. The gate structure is across the semiconductor fin and the dielectric fin structure, wherein a portion of the gate structure in contact with the isolation layer has a first width, and another portion of the gate structure in contact with the top dielectric fin has a second width greater than the first width.