Dielectric Fin Gate Cut Structure for Lower-Aspect-Ratio Openings
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Solution Overview
Problem
Challenges in semiconductor fabrication arise from high aspect ratios in gate openings, leading to difficulties in forming gate cut isolation structures, which affect the reliability and yield of semiconductor devices.
Innovation Solution
The formation of a dielectric fin structure between semiconductor fin structures, accompanied by a gate cut isolation structure, reduces the aspect ratio of gate openings, enhancing the formation of gate cut isolation structures and improving the reliability and yield of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used without dielectric fin structures, then the gate openings have high aspect ratios, but this makes it difficult to form gate cut isolation structures and reduces manufacturing yield
Solution Approach 1:
The patent introduces a dielectric fin structure that segments the gate opening into multiple smaller openings. By placing the dielectric fin between adjacent semiconductor fins, the single high aspect ratio gate opening is divided into separate lower aspect ratio openings, making it easier to form gate cut isolation structures and improving manufacturing precision
Solution Approach 2:
The dielectric fin structure acts as an intermediary element between adjacent semiconductor fins. This intermediate structure provides mechanical support and reduces the effective depth of gate openings, thereby lowering the aspect ratio and facilitating the formation of gate cut isolation structures without directly modifying the semiconductor fins themselves
2Reliability
If high aspect ratio gate openings are used, then device density can be maintained, but reliability and yield of semiconductor devices decrease
Solution Approach 1:
The dielectric fin structure is formed in advance before gate cut isolation structures are created. This preliminary action of adding the dielectric fin reduces the aspect ratio of gate openings beforehand, ensuring that subsequent isolation structure formation can be completed successfully and improving overall manufacturing yield and device reliability
Data Source
AI summary
A semiconductor structure includes a substrate, an isolation structure over the substrate, a first semiconductor fin protruding from the substrate and through the isolation structure, a second semiconductor fin protruding from the substrate and through the isolation structure, a dielectric fin between the first semiconductor fin and the second semiconductor fin, a first gate stack across the first semiconductor fin, a first gate spacer extending along a sidewall of the first gate stack, a second gate stack across the second semiconductor fin, a second gate spacer extending along a sidewall of the second gate stack, and a gate cut feature disposed over a top surface of the dielectric fin. Top surfaces of the first and second semiconductor fins and the top surface of the dielectric fin are coplanar. The gate cut feature separates the first gate stack from the second gate stack.