Dielectric Fin Structures for Gate Support in FinFET Isolation
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Solution Overview
Problem
Conventional planar field effect transistors (FETs) have reached fundamental scaling limits, and there is a need for unconventional geometries to continue device performance improvements, particularly in preventing gate structures from lifting off the substrate due to undercutting during epitaxial growth processes.
Innovation Solution
The use of dielectric fin structures to support gate structures over isolation regions of a semiconductor substrate, where fin trenches are formed and filled with dielectric material to prevent gate flop over, and epitaxial source and drain regions are formed on semiconductor fin structures with gate structures on both semiconductor and dielectric fin portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar FET scaling is continued, then device performance improvement is achieved, but fundamental scaling limits are reached
Solution Approach 1:
The patent transitions from planar FET geometry to FinFET geometry by introducing vertical fins that extend upward from the substrate. This dimensional change from 2D planar to 3D vertical structure increases the effective channel area and improves gate control without further reducing the lateral footprint, thereby overcoming scaling limits while maintaining device performance improvements
2Reliability
If epitaxial growth process is used to form source and drain regions, then device performance is improved, but gate structures lift off the substrate due to undercutting
Solution Approach 1:
The patent applies a mandrel layer and spacer layer formulation before epitaxial growth that prevents undercutting from occurring. The spacer layer is formed with controlled thickness and material properties that prevent the epitaxial material from detaching the gate structure, thereby maintaining gate stability while still enabling performance improvements from the epitaxial growth process
Solution Approach 2:
The patent introduces intermediate layers (mandrel layer and spacer layer) between the substrate and the epitaxial source/drain regions. These intermediate structures act as mediators that prevent direct contact between the epitaxial material and the gate structure, eliminating the undercutting mechanism while allowing the epitaxial growth to proceed for performance enhancement
3Reliability
If FinFET geometry is adopted, then device performance improvement continues, but manufacturing complexity increases
Solution Approach 1:
The patent segments the fin structure into distinct functional layers: semiconductor fin layer, mandrel layer, and spacer layer. Each layer serves a specific purpose and can be processed independently, which simplifies the manufacturing of the complex FinFET geometry by breaking it down into manageable fabrication steps while maintaining the performance benefits of the 3D structure
Data Source
AI summary
A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.