Dielectric Fin Liner for GAA Gate and Spacer Integrity
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Solution Overview
Problem
GAA finFET devices face challenges such as sub-channel formation, reduced gate control due to protrusion of isolation layers, voids or seams in spacer structures, and uniformity issues during nanosheet/nanowire formation, which affect performance and manufacturing efficiency.
Innovation Solution
A semiconductor device with a dielectric liner is introduced, which includes a fin structure, an isolation layer between stacked fin structures and the bottom fin portion, and a spacer structure in contact with the dielectric liner, improving the formation window of the replacement metal gate and preventing over etching, while enhancing the uniformity of semiconductor layers through a two-step process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If isolation layers are used to separate stacked fin structures, then electrical isolation is improved, but gate control is reduced due to protrusion into the gate area
Solution Approach 1:
A dielectric liner is introduced as an intermediary layer between the isolation layer and the stacked fin structures. This mediator prevents the isolation layer from protruding into the gate area while maintaining electrical isolation functionality, thus resolving the contradiction between isolation effectiveness and gate control.
Solution Approach 2:
The isolation structure is segmented into multiple components: the isolation layer itself and the dielectric liner that caps it. This segmentation allows the isolation layer to perform its electrical isolation function while the dielectric liner prevents protrusion, separating the conflicting functions into distinct structural elements.
2Manufacturing precision
If spacer structures are formed to define gate regions, then device geometry is improved, but voids or seams form in the spacer structures
Solution Approach 1:
The dielectric liner acts as a mediator between the spacer structure and the underlying layers. It provides a stable interface that prevents voids and seams from forming during spacer formation, ensuring both geometric precision and structural integrity.
Solution Approach 2:
The dielectric liner is deposited beforehand to cushion and protect the interface where voids and seams would otherwise form. This preventive measure ensures continuous, defect-free spacer structures while maintaining accurate device geometry.
3Productivity
If nanosheet/nanowire formation processes are used to create channel structures, then device performance is improved, but uniformity issues occur during formation
Solution Approach 1:
The dielectric liner serves as a mediator that provides a uniform foundation for nanosheet/nanowire formation. It ensures consistent spacing and alignment during the formation process, thereby achieving both high device performance and uniform layer quality.
Data Source
AI summary
The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.