Dielectric Fin Anti-Fuse Memory Cells for Stable PUF Signatures
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Solution Overview
Problem
Existing anti-fuse memory technologies face challenges in efficiently generating unique Physically Unclonable Function (PUF) signatures due to manufacturing variability, which affects the reliability and security of authentication and secret key storage.
Innovation Solution
The proposed solution involves designing anti-fuse memory cells with a pair of programming transistors and multiple pairs of reading transistors, where the programming transistors are formed with a gate-all-around (GAA) transistor configuration and isolated by a dielectric fin structure. This configuration allows for random breakdown of one programming transistor over the other, generating a unique PUF bit and signature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manufacturing variability is increased to generate unique PUF signatures, then security and authentication capability are improved, but reliability and consistency of memory operation deteriorate
Solution Approach 1:
The memory device is divided into multiple independently addressable memory cells, each capable of generating its own PUF signature. The dielectric fin structure segments the programming transistor channels, creating isolated regions that contribute to unique signature generation while maintaining individual cell reliability through separate operation.
Solution Approach 2:
The dielectric fin structure introduces local variation in the programming transistor characteristics at specific locations within each memory cell. This local quality differentiation enables unique PUF signatures while the overall memory cell structure maintains consistent and reliable operation through standardized cell design.
2Speed
If gate-all-around transistor configuration is used to improve reading and programming performance, then read margin and speed are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate structure transitions from planar to three-dimensional gate-all-around configuration, wrapping around the channel in multiple dimensions. This dimensional change provides superior electrostatic control and faster switching performance while the dielectric fin structure simplifies the overall fabrication by providing a natural template for the GAA structure.
Solution Approach 2:
The dielectric fin structure serves as an intermediary element that facilitates the formation of gate-all-around transistors. It acts as a structural template and isolation element that simplifies the complex process of creating GAA devices by providing predefined separation and support structures.
3Adaptability or versatility
If dielectric fin structure is introduced to isolate programming transistors, then PUF signature generation capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric fin structure is formed early in the fabrication process, before the programming transistors are fully constructed. This preliminary action establishes the isolation framework that guides subsequent processing steps, reducing the precision requirements for later stages by providing a pre-defined structural template.
Solution Approach 2:
The dielectric fin structure functions as a temporary but critical fabrication feature that enables PUF signature generation. Once the transistors are formed and isolated, the fins have served their primary purpose of enabling unique signature generation while maintaining manufacturing feasibility through standard dielectric processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reading/programming performance, improves the read margin, reduces power consumption, and extends the lifetime of the memory system by allowing for efficient generation of unique PUF signatures, thereby improving authentication and security.
Implementation Method 1
The programming transistor may be broken down by applying a high voltage to a gate of the programming transistor
Data Source
AI summary
A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.