Hybrid Dielectric Fin Deposition for Etch-Resistant Fin Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating more components into smaller areas due to limitations in feature size reduction, which affects the manufacturing of FinFETs and other semiconductor devices, particularly in forming reliable dielectric layers and fins within isolation regions.
Innovation Solution
A method involving the formation of a hybrid dielectric fin using a blocking layer and a bulk material, where precursor materials are pulsed in controlled sequences within a deposition chamber to achieve specific compositions and thicknesses, enhancing the structural integrity and etch resistance of the fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing reliability deteriorates due to difficulties in forming reliable dielectric layers and fins
Solution Approach 1:
The dielectric fin structure is segmented into multiple functional layers: a blocking layer (first dielectric material) and a bulk material layer (second dielectric material). This segmentation allows each layer to perform its specific function - the blocking layer prevents chemical penetration and the bulk material provides structural support - thereby maintaining manufacturing reliability while enabling reduced feature sizes for higher integration density.
Solution Approach 2:
The patent employs composite dielectric materials with different properties in different layers. The blocking layer uses a material with specific etch resistance and chemical stability, while the bulk material uses a different dielectric material optimized for electrical isolation. This composite structure resolves the contradiction by combining materials with complementary properties to achieve both small dimensions and high reliability.
2Ease of manufacture
If conventional dielectric materials are used in isolation regions, then the manufacturing process is simple, but etch rates are too high allowing chemical penetration into underlying structures
Solution Approach 1:
The blocking layer acts as an intermediary barrier between the conventional dielectric material and the underlying semiconductor structures. This intermediate layer prevents harmful chemical penetration while allowing the rest of the manufacturing process to remain relatively simple, as the blocking layer can be deposited using standard deposition techniques followed by planarization.
Solution Approach 2:
Instead of using a single uniform dielectric material throughout the isolation region, the patent applies different dielectric materials with specific properties to different locations: the blocking layer with high etch resistance is applied where chemical penetration must be prevented, while other areas use conventional dielectric materials. This local differentiation resolves the contradiction between simplicity and chemical resistance.
3Productivity
If feature sizes are reduced to increase integration density, then more components fit in a given area, but etch rate control becomes more difficult affecting fin structure integrity
Solution Approach 1:
The patent changes the material parameters of the dielectric fin structure by using different dielectric materials with different etch rates in different layers. The blocking layer has specifically selected etch resistance parameters that allow precise control during etching processes, enabling accurate fin formation even at reduced feature sizes. This parameter optimization resolves the contradiction between high integration density and etch rate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the integration density and reliability of semiconductor devices by reducing etch rates and preventing chemical penetration, leading to better device performance and yield.
Implementation Method 1
depositing a first dielectric material within the opening, the depositing the first dielectric material including: pulsing a first precursor material for a first time of between about 20 seconds and about 120 seconds; pulsing a second precursor material for a second time of between about 70 seconds and about 200 seconds
Data Source
AI summary
A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.