Dielectric Fin Isolation Structure for Source/Drain Short Prevention

Solution Overview

Problem

Existing dielectric isolation structures in semiconductor integrated circuits, particularly for multi-bridge-channel transistors, are inadequate in preventing undesirable electrical shorts between adjacent source/drain features, which can lead to performance issues and manufacturing challenges.

Innovation Solution

The development of a dielectric fin structure comprising a bottom portion with an outer etch-resistant metal oxide layer and an inner low-dielectric-constant dielectric material layer, and a top helmet layer with a higher etch resistance, which integrates seamlessly with the fabrication of multi-bridge-channel transistors to prevent source/drain feature merging and facilitate gate segmentation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional dielectric isolation structures are used, then fabrication process is simple, but source/drain features merge causing undesirable electrical connections

Engineering Contradiction:

Improveelectrical isolation between source/drain featuresVSAvoidisolation structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure uses a composite dielectric fin comprising multiple layers with different dielectric constants and etch resistances. The first dielectric layer has lower dielectric constant than the second dielectric layer, creating a composite structure that provides both electrical isolation and mechanical stability. This composite approach resolves the contradiction by achieving reliable electrical isolation through material composition rather than structural complexity.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The dielectric fin structure applies local quality by having different regions of the isolation structure with different properties. The first dielectric layer provides low-k electrical isolation in the upper region, while the second dielectric layer provides etch resistance in the lower region. This localized differentiation allows each layer to perform its specific function optimally, achieving reliable isolation without overall structural complexity.

Inventive Principle:

Principle #3Local quality

2Productivity

If multi-gate devices are scaled down, then production efficiency increases, but manufacturing complexity increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidmanufacturing process complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The dielectric fin isolation structure is formed preliminarily before source/drain feature formation. By pre-establishing the isolation fins with appropriate etch resistance, subsequent epitaxial growth and source/drain processing steps are simplified and more controllable. This preliminary action enables efficient scaling to smaller technology nodes while managing manufacturing complexity through structured process sequencing.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If dielectric fins are made taller, then isolation effectiveness improves, but gate structure formation becomes more difficult

Engineering Contradiction:

Improveisolation effectivenessVSAvoidgate structure formation ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The dielectric fin structure applies local quality by having different regions of the isolation structure with different properties. The first dielectric layer provides low-k electrical isolation in the upper region, while the second dielectric layer provides etch resistance in the lower region. This localized differentiation allows each layer to perform its specific function optimally, achieving reliable isolation without overall structural complexity.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The isolation structure uses a composite dielectric fin comprising multiple layers with different dielectric constants and etch resistances. The first dielectric layer has lower dielectric constant than the second dielectric layer, creating a composite structure that provides both electrical isolation and mechanical stability. This composite approach resolves the contradiction by achieving reliable electrical isolation through material composition rather than structural complexity.

Inventive Principle:

Principle #40Composite materials

Data Source

PatentUS20230268384A1Isolation structure for transistors

Publication Date: 2023.08.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure according to the present disclosure includes a base fin over a substrate, a stack of nanostructures disposed directly over the base fin, a gate structure wrapping around each of the stack of nanostructures, an isolation feature disposed over the substrate and adjacent the base fin, and a dielectric fin disposed directly on the isolation feature. The dielectric includes in a bottom portion, a middle layer over the bottom portion and a top layer over the middle layer. The bottom portion includes an outer layer and an inner layer spaced apart from the gate structure and the isolation feature by the outer layer. The middle layer is in direct contact with top surfaces of the inner layer and the outer layer. The dielectric constant of the top layer of the dielectric fin is greater than the dielectric constant of the middle layer.