Dielectric Fin SRAM Cell Layout to Prevent Source/Drain Bridging
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Solution Overview
Problem
As semiconductor devices miniaturize, the adjacent source/drain structures of transistors can connect during the epitaxial process, leading to an undesirable bridge problem that affects the performance and operation speeds of SRAM cells.
Innovation Solution
Incorporating dielectric fins between adjacent fins to prevent the bridge problem by allowing source/drain structures to contact the dielectric fins, thereby reducing contact resistance and enhancing transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain structures are allowed to reach maximum sizes for optimal transistor performance, then transistor performance is improved, but adjacent source/drain structures connect during epitaxial process causing bridge problem
Solution Approach 1:
The patent divides the continuous fin structure into separate fins by introducing dielectric fins between adjacent semiconductor fins. This segmentation prevents the source/drain structures of adjacent transistors from connecting during the epitaxial process, thereby solving the bridge problem while allowing each transistor's source/drain structures to reach their maximum sizes for optimal performance
Solution Approach 2:
Dielectric fins are introduced as intermediary structures between adjacent semiconductor fins. These dielectric fins act as physical barriers that prevent unwanted electrical connection between adjacent source/drain structures during the epitaxial growth process, while not interfering with the performance of individual transistors
2Productivity
If device miniaturization is pursued to reduce power consumption and increase functionality, then power consumption is reduced and functionality is increased, but adjacent source/drain structures are more likely to connect causing bridge problem
Solution Approach 1:
By segmenting the fin structure with dielectric fins, the patent enables continued device miniaturization and increased transistor density without suffering from bridge problems. The segmentation maintains adequate isolation between adjacent structures even as overall device dimensions are reduced
Solution Approach 2:
The patent introduces dielectric fins that extend in the vertical dimension between adjacent horizontal fins. This three-dimensional approach provides effective isolation without consuming additional planar area, thereby enabling continued miniaturization and increased functionality per unit area
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin and a second dielectric fin over a substrate, a first semiconductor fin between the first dielectric fin and the second dielectric fin, and an insulating liner surrounding a lower portion of the first dielectric fin, a lower portion of the first semiconductor fin, and a lower portion of the second dielectric fin. The semiconductor structure also includes a first gate electrode surrounding an upper portion of the first dielectric fin and an upper portion of the first semiconductor fin.