Dielectric Fins With Air Gaps for Lower Gate-to-S/D Capacitance
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Solution Overview
Problem
The challenge in the semiconductor industry is to effectively isolate adjacent metal gate electrodes and source/drain electrodes in highly integrated circuits while reducing coupling capacitance, which is complex due to the increasing miniaturization of ICs and complexity of manufacturing processes.
Innovation Solution
The use of dielectric fins with air gaps formed by combining wafer frontside and backside processes, where a sacrificial layer is removed and sealed with a dielectric material to create air gaps within the fins, reducing coupling capacitance between adjacent metal gates and S/D features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation structures are used to isolate adjacent metal gate electrodes and source/drain electrodes, then isolation is achieved, but coupling capacitance between adjacent structures remains high
Solution Approach 1:
The patent introduces air gaps (porous structures) within the dielectric fin material to reduce the effective dielectric constant between adjacent metal gates and source/drain electrodes. This porous dielectric fin structure lowers coupling capacitance while maintaining electrical isolation, directly addressing the contradiction between isolation effectiveness and coupling capacitance reduction.
2Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then productivity increases, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the dielectric fin structure into multiple functional layers including sacrificial layers, air gap regions, and sealed dielectric portions. This segmentation allows each layer to serve specific purposes in the manufacturing process, enabling scalable fabrication that maintains productivity while managing complexity through modular structure design.
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial layers and air gap structures before final device assembly. These pre-formed structures guide subsequent manufacturing steps and enable self-aligned processes, reducing the need for complex alignment procedures and maintaining manufacturing efficiency despite device miniaturization.
3Object-generated harmful factors
If dielectric fins with air gaps are formed using combined wafer frontside and backside processes, then coupling capacitance is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming air gaps and dielectric fins in the depth direction rather than only in the lateral plane. This three-dimensional structuring reduces coupling capacitance between adjacent structures while the self-aligned nature of the vertical formation processes helps manage manufacturing complexity.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures that facilitate the formation of air gaps. These sacrificial layers are temporarily present during manufacturing to define air gap regions, then selectively removed to create the final porous dielectric fin structure, simplifying the overall manufacturing sequence.
Data Source
AI summary
A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.