Dielectric Gate Isolation in FinFETs to Cut Parasitic Capacitance
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Solution Overview
Problem
Conventional gate isolation sections in semiconductor devices composed of conductive materials lead to significant parasitic capacitance, increasing power consumption and reducing operation speed.
Innovation Solution
Formation of dielectric gate isolation sections using dielectric materials, which reduces parasitic capacitance and prevents gate-to-drain leakage, achieved by modifying the existing cut poly (CPO) process without additional patterning or area penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive gate isolation sections are used, then gate isolation function is achieved, but parasitic capacitance increases leading to higher power consumption and reduced operation speed
Solution Approach 1:
The patent changes the material parameter of the gate isolation section from conductive material to dielectric material. This fundamental material parameter change eliminates parasitic capacitance between the gate isolation section and adjacent conductive elements, thereby reducing power consumption while maintaining the gate isolation function.
Solution Approach 2:
The patent uses a dielectric material that can be easily deposited and removed, replacing the conventional conductive material. The dielectric gate isolation section serves its isolation function and can be integrated into the fabrication process without requiring complex additional steps, effectively providing a low-cost solution to reduce parasitic capacitance.
2Reliability
If conventional conductive gate isolation sections are used, then gate isolation function is achieved, but operation speed is reduced due to parasitic capacitance
Solution Approach 1:
The patent changes the material parameter of the gate isolation section from conductive material to dielectric material. This fundamental material parameter change eliminates parasitic capacitance between the gate isolation section and adjacent conductive elements, thereby reducing power consumption while maintaining the gate isolation function.
3Speed
If dielectric gate isolation sections are formed by modifying CPO process, then parasitic capacitance is reduced and operation speed is enhanced, but process complexity increases
Solution Approach 1:
The patent merges the gate isolation section formation with the existing cut poly (CPO) process flow. By integrating the dielectric material deposition and patterning steps into the conventional CPO process, the patent achieves reduced parasitic capacitance without requiring completely new fabrication equipment or processes, thereby limiting the increase in process complexity.
Solution Approach 2:
The dielectric material used in the gate isolation section serves multiple functions: it provides gate isolation, reduces parasitic capacitance, and can be integrated with the existing CPO process flow. This multi-functionality reduces the need for additional specialized process steps, thereby limiting the increase in overall process complexity.
4Use of energy by moving object
If dielectric gate isolation sections are formed, then parasitic capacitance is reduced, but manufacturing process becomes more complex
Solution Approach 1:
The patent merges the gate isolation section formation with the existing cut poly (CPO) process flow. By integrating the dielectric material deposition and patterning steps into the conventional CPO process, the patent achieves reduced parasitic capacitance without requiring completely new fabrication equipment or processes, thereby limiting the increase in process complexity.
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. In one example, a semiconductor device includes: a substrate, a fin formed on the substrate, a gate structure formed on the fin, a metal contact formed on the fin and adjacent to the gate structure. The fin extends along a first horizontal direction, the gate structure and the metal contact extend along a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction. The gate structure further includes a gate electrode coupled to the fin and a dielectric gate isolation section separated from the gate electrode. The dielectric gate isolation section includes a dielectric material. A portion of the dielectric gate isolation section is aligned with a portion of the metal contact adjacent and proximate to the dielectric gate isolation section in the first horizontal direction.