Dielectric Helmet Structures for Semiconductor Interconnects

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Solution Overview

Problem

The challenge in fabricating interconnects for integrated circuits lies in achieving sufficient electrical isolation and low resistance while maintaining a densely packed layout, as existing methods struggle with controlling airgap placement and dielectric intrusion, which can lead to increased parasitic capacitance and performance degradation.

Innovation Solution

The use of dielectric helmet structures over conductive traces, which act as a height buffer to ensure the dielectric layer remains above the interconnects, creating an increased airgap and reducing parasitic capacitance, and can be used to form high-aspect ratio features by sequential deposition and etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dielectric material is deposited to fill spaces between conductive traces, then electrical isolation is improved, but parasitic capacitance increases due to dielectric intrusion

Engineering Contradiction:
Improveelectrical isolationVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the dielectric material from the spaces between conductive traces by creating airgaps, removing the harmful dielectric intrusion that causes parasitic capacitance while maintaining electrical isolation through the airgap structure

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different material properties locally by using airgaps (devoid of material) in specific regions between conductive traces to minimize parasitic capacitance, while using dielectric material in other regions for electrical isolation, creating a spatially varying structure optimized for both functions

Inventive Principle:
Principle #3Local quality

2Productivity

If conductive traces are densely packed to increase interconnect density, then productivity is improved, but manufacturing precision deteriorates due to difficulty in controlling airgap placement

Engineering Contradiction:
Improveinterconnect densityVSAvoidairgap placement control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary action by forming mandrel structures and applying selective deposition techniques before final airgap creation, ensuring precise airgap placement is achieved through pre-positioned structures that guide subsequent material deposition and removal processes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses mandrel structures as intermediary elements that facilitate precise airgap formation. These mandrels serve as temporary structures that define the exact location and shape of airgaps, enabling controlled material removal to create airgaps with high manufacturing precision even in densely packed interconnect configurations

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-generated harmful factors

If airgap is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases due to additional helmet structures

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidstructure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality to the helmet structures, which simultaneously serve as etch masks for defining airgap regions and as structural elements that can be selectively removed to create the airgaps. This dual function reduces the need for separate process steps and structures, thereby reducing overall device complexity despite the increased airgap size

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes parasitic capacitance and allows for the formation of high-aspect ratio interconnects with low resistance, maintaining high packing density and performance.

Implementation Method 1

forming dielectric helmet structures over top surfaces of the conductive traces

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS11646266B2Helmet structures for semiconductor interconnects
Publication Date: 2023.05.09 INTEL CORP
  • US11646266B2 patent drawing
  • US11646266B2 patent drawing
  • US11646266B2 patent drawing

AI summary

Interconnect structures are disclosed. An example includes conductive traces over a first dielectric layer, dielectric helmet structures over top surfaces of the conductive traces, and a second dielectric layer over the helmet structures. Spaces between adjacent ones of conductive traces are devoid of material. A bottom surface of the second dielectric layer is between top surfaces of the dielectric structures and bottom surfaces of the helmet structures, or co-planar with the top surface of the helmet structures, but the airgap extends above tops of the conductive traces. Another example includes a dielectric adjacent to upper sections but not lower sections of conductive traces, so as to provide airgaps between adjacent lower sections. Alternatively, a first dielectric material is adjacent the upper sections and a second compositionally different dielectric material is adjacent the lower sections. In either case, the sidewalls of the upper sections of the interconnect features may include scalloping.