Interlayer Dielectric Implantation to Close Via Gaps and Cracks
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in processes that lead to gaps and cracks between conductive materials and interlayer dielectrics, causing parasitic resistance and damage during planarization processes.
Innovation Solution
A high ion beam current is used for pre-amorphization and post-silicide implantations to fill conductive features in interlayer dielectrics, inducing compression stress to close gaps and cracks, and a subsequent implantation process with neutral elements like germanium expands the dielectric materials to further secure the connection, preventing damage during chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but gaps and cracks form between conductive materials and interlayer dielectrics causing parasitic resistance
Solution Approach 1:
The patent applies preliminary action by performing pre-amorphization implantation before filling conductive features. This pre-treatment modifies the dielectric material structure in advance to prevent gap and crack formation during subsequent planarization processes, thereby eliminating parasitic resistance pathways while maintaining high integration density
Solution Approach 2:
The patent utilizes parameter changes by controlling ion beam implantation energy, dose, and species to achieve desired dielectric material modifications. By adjusting these parameters, the dielectric constant and mechanical properties of the interlayer dielectric are optimized to prevent gap formation at conductor-dielectric interfaces, resolving the parasitic resistance issue
2Reliability
If high ion beam current is used for implantation to close gaps and cracks, then parasitic resistance is reduced, but production time increases
Solution Approach 1:
The pre-amorphization implantation is performed at high ion beam current to rapidly create compression stress and close gaps before the conductive fill material is deposited. This preliminary high-current treatment prevents gap formation in advance, eliminating the need for subsequent high-current treatments and reducing total production time
Solution Approach 2:
The patent employs periodic action by using multiple implantation steps with alternating conditions: a first implantation at high ion beam current to close gaps rapidly, followed by a second implantation at lower current to fine-tune the dielectric properties. This periodic approach balances speed and quality, reducing overall production time while maintaining low parasitic resistance
3Reliability
If multiple implantation steps are performed to eliminate gaps and cracks, then connection reliability is improved, but process complexity increases
Solution Approach 1:
The pre-amorphization implantation serves as a preliminary action that creates compression stress and closes gaps before conductive material deposition. This single preliminary step achieves the primary goal of gap elimination, making subsequent implantation steps optional rather than mandatory, thereby reducing overall process complexity while maintaining connection reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces parasitic resistance and prevents loss of conductive structures by eliminating gaps and cracks, ensuring reliable connections and reducing production time and costs through high throughput implantation processes.
Implementation Method 1
A method for forming a conductive feature in a dielectric layer includes implanting ions into a semiconductor substrate
Implementation Method 2
The implantation can create compression stress between the conductive fill material and the interlayer dielectric to close gaps and cracks between the materials
Data Source
AI summary
Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.