Dielectric Inner Spacers for GAA Transistors
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Solution Overview
Problem
Existing methods for fabricating inner spacers in gate-all-around (GAA) transistors face challenges in reducing parasitic capacitance without shortening the effective channel length, and in providing sufficient etching resistance during the manufacturing process.
Innovation Solution
The method involves forming inner spacers with a dual-layer dielectric structure, where a high-k dielectric layer is used on the sidewalls of the metal gate stack and a low-k dielectric layer or air gap is formed over it, embedded within the epitaxial source/drain features, to reduce parasitic capacitance while maintaining the channel length and withstanding etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If inner spacers are made thicker to reduce parasitic capacitance, then parasitic capacitance decreases, but effective channel length is shortened
Solution Approach 1:
The patent applies local quality by using different dielectric materials with different properties at different locations within the inner spacer structure. Specifically, a first dielectric material with higher etching resistance is used in the lower portion of the inner spacer, while a second dielectric material with lower dielectric constant is used in the upper portion. This allows the lower portion to provide sufficient etching resistance during gate replacement processes, while the upper portion effectively reduces parasitic capacitance between the gate stack and source/drain features, without requiring the entire spacer to be excessively thick.
2Reliability
If inner spacers are made with higher etching resistance material, then etching resistance increases, but parasitic capacitance increases
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through a vertically stratified dielectric structure. The first dielectric material (e.g., silicon nitride or silicon oxynitride) with high etching resistance is positioned in the lower portion of the inner spacer where it is most needed to protect against etching damage during gate replacement. The second dielectric material (e.g., silicon oxide or low-k material) with lower dielectric constant is positioned in the upper portion where its primary function is to reduce parasitic capacitance. This spatial differentiation allows each material to optimize its specific function without compromising the other.
Solution Approach 2:
The patent employs composite materials by combining two different dielectric materials within a single inner spacer structure. The composite structure consists of a first dielectric layer and a second dielectric layer with different material compositions and properties. This composite approach enables the inner spacer to simultaneously achieve high etching resistance (from the first dielectric material) and low parasitic capacitance (from the second dielectric material), resolving the contradiction between these two opposing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between the metal gate stack and source/drain features, minimizes channel length shortening, and enhances the reliability of the GAA transistors by providing adequate etching resistance during the gate replacement processes.
Implementation Method 1
the first layer including a material having a higher etching resistance than the material of the second dielectric layer
Implementation Method 2
reduce parasitic capacitance between the metal gate stack and source/drain features
Implementation Method 3
the second layer having a lower dielectric constant than the first dielectric layer
Data Source
AI summary
A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.