Dielectric Interlayer Void Prevention in Closely Spaced Lines
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Solution Overview
Problem
The existing deposition techniques for forming dielectric interlayers in semiconductor devices with closely spaced lines, such as those in the 90 nm technology node, face challenges in completely filling empty spaces between lines, leading to voids and increased defect rates, especially when the distance between lines is 200 nm or less, which affects the reliability and cost-effectiveness of the manufacturing process.
Innovation Solution
A method involving the formation of a first silicon dioxide layer using thermal CVD or high-density plasma CVD for superior gap filling, followed by a second layer using plasma enhanced CVD, and subsequent planarization, to reduce the aspect ratio of empty spaces and enable reliable deposition of the bulk dielectric material with established plasma enhanced CVD techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If well-established high rate PECVD techniques are used for silicon dioxide deposition, then deposition rate and productivity are improved, but gap-fill capability deteriorates leading to voids in closely spaced line structures
Solution Approach 1:
The dielectric interlayer formation process is segmented into multiple deposition steps: first forming a mandrel layer, then a first dielectric layer, followed by a second dielectric layer, and finally a third dielectric layer. Each layer serves a specific function - the mandrel defines the pattern, the first dielectric fills gaps, and subsequent dielectric layers complete the interlayer formation. This segmentation allows each step to be optimized independently, resolving the contradiction between deposition rate and gap-fill capability.
Solution Approach 2:
The mandrel layer is formed preliminarily to define the pattern and create a template for subsequent dielectric layer deposition. This preliminary action establishes the structural framework that guides the gap-filling process, enabling the first dielectric layer to be deposited in a controlled manner that ensures complete filling of empty spaces before higher rate deposition techniques are applied in later stages.
2Reliability
If deposition techniques with superior gap fill capabilities are used, then void formation is reduced, but deposition rate and productivity decrease
Solution Approach 1:
The deposition process is divided into segments where different techniques are applied at different stages. The first dielectric layer uses a technique with superior gap-fill capability to ensure void-free filling of the mandrel-defined spaces. Subsequent second and third dielectric layers use well-established high rate PECVD techniques that provide high productivity. This segmentation allows the system to achieve both reliability in the critical gap-filling stage and high productivity in the bulk deposition stages.
Solution Approach 2:
Different deposition techniques are applied to different regions and stages of the process based on local requirements. In the early stage where gap-filling is critical (first dielectric layer), a technique with superior gap-fill capability is used. In later stages where bulk material deposition is the priority (second and third dielectric layers), high rate PECVD techniques are used. This local optimization resolves the contradiction between reliability and productivity.
3Area of stationary object
If the distance between closely spaced lines is reduced to increase circuit density, then chip area utilization is improved, but the aspect ratio of empty spaces increases making complete filling more difficult
Solution Approach 1:
The mandrel layer is formed preliminarily with a specific pattern and dimensions that define the empty spaces to be filled. By controlling the mandrel geometry, the aspect ratio of the resulting empty spaces is optimized before dielectric deposition begins. This preliminary structuring enables complete filling even when line distances are reduced for higher circuit density.
Solution Approach 2:
The dielectric interlayer is segmented into multiple layers (first, second, and third dielectric layers) with different functions. The first dielectric layer specifically addresses the gap-filling challenge by using a deposition technique with superior gap-fill capability tailored to the mandrel-defined geometry. This segmentation allows the process to handle the increased aspect ratio challenges posed by closely spaced lines while maintaining high chip area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the aspect ratio of empty spaces, minimizing voids and defect rates, while maintaining high deposition rates and reducing production costs by allowing the use of well-established process recipes for the majority of the dielectric material deposition.
Implementation Method 1
depositing a first layer of silicon dioxide over the device layer by one of a thermal CVD process based on TEOS and a high density plasma CVD process
Implementation Method 2
a second layer of silicon dioxide is deposited on the first layer by a PECVD process
Implementation Method 3
the second layer is planarized by chemical mechanical polishing
Data Source
AI summary
By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces between closely spaced lines on the order of 200 nm or less. Moreover, the bulk silicon dioxide material is deposited by well-established plasma enhanced CVD techniques, thereby providing the potential for using well-established process recipes for the subsequent CMP process, so that production yield and cost of ownership may be maintained at a low level.