Dielectric Chiplet Interposer Stitching for Low-Warpage Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high integration density and reduced stress concentration, particularly in the use of silicon substrates which can lead to warpage and delamination issues, while also limiting the footprint of interposers due to high stress modulus.
Innovation Solution
The use of a dielectric fill layer as a substrate instead of a silicon layer, combined with a carrier substrate that can be removed, and a redistribution structure formed through multiple side-by-side patterning processes, allowing for a stitching process to create larger metallization patterns and reduce stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a silicon substrate is used in the interposer, then the interposer provides structural support and electrical connectivity, but the high stress modulus of silicon causes warpage and delamination issues
Solution Approach 1:
The patent changes the material parameter of the interposer from silicon (high stress modulus) to organic substrate material (lower stress modulus). This parameter change reduces the stress concentration in the interposer, thereby minimizing warpage and delamination risks while maintaining structural support functionality.
2Strength
If a silicon substrate is used in the interposer, then the interposer provides structural support, but the footprint of the interposer is limited due to high stress modulus
Solution Approach 1:
The patent changes the material parameter from silicon to organic substrate material with lower stress modulus. This enables the interposer to achieve a larger footprint area while maintaining adequate structural support, as the reduced stress concentration allows for extended dimensions without excessive warpage or delamination.
3Ease of manufacture
If traditional light mask sizes are used for patterning, then the manufacturing process is simple, but the metallization patterns are limited in size
Solution Approach 1:
The patent segments the patterning process into multiple steps, using multiple light masks to create metallization patterns that exceed the size of a single light mask. The process involves forming initial patterns, then using additional masks to extend and combine patterns, achieving large-scale metallization while maintaining manufacturing feasibility through stepwise construction.
Data Source
AI summary
Embodiments include packages and methods for forming packages which include interposers having a substrate made of a dielectric material. The interposers may also include a redistribution structure over the substrate which includes metallization patterns which are stitched together in a patterning process which includes multiple lateral overlapping patterning exposures.