Dielectric Isolated FinFET With Wider Source/Drain Epitaxy Base
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Solution Overview
Problem
The challenge in improving FinFET performance lies in maximizing channel strain while maintaining conventional embedded source/drain epitaxy quality, which is compromised due to narrow seed layers for epitaxial growth in dielectric isolated FinFETs.
Innovation Solution
A semiconductor structure with a wider fin base isolated by a dielectric layer allows for epitaxial growth of source/drain structures outside the gate area, enhancing dopant incorporation and strain, formed by etching a sacrificial spacer to increase the fin base width and filling cavities with dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric isolation is used in FinFET to maintain short-channel control, then short-channel control is improved, but the seed layer width for epitaxial growth becomes narrow compromising source/drain epitaxy quality
Solution Approach 1:
The fin base is segmented into two distinct width regions: a narrow fin structure width (W1) for maintaining short-channel control, and a wider fin base width (W2) for enabling quality epitaxial growth. This segmentation is achieved by forming a dielectric isolation layer that laterally isolates the fin structure from the fin base edges, allowing the fin base to extend beyond the fin structure boundaries.
Solution Approach 2:
The solution transitions from a single-dimension constraint (fin width) to a two-dimension structure by introducing lateral extension in the fin base width. The dielectric isolation layer enables the fin base to extend laterally beyond the fin structure, creating a wider epitaxial growth area without affecting the vertical fin height or channel width, thus resolving the contradiction between narrow channel requirement and wide epitaxy requirement.
2Manufacturing precision
If the fin base width is increased to improve epitaxial growth, then source/drain epitaxy quality is improved, but the device area and complexity increase
Solution Approach 1:
A dielectric isolation layer is introduced as an intermediary element between the fin structure and the surrounding environment. This isolation layer serves multiple functions: it enables lateral extension of the fin base for improved epitaxy, provides electrical isolation, and maintains structural integrity. The intermediary layer allows the fin base to extend beyond the fin structure without directly increasing device complexity, as the isolation layer is formed using standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves source/drain epitaxy quality and strain enhancement, overcoming the limitations of narrow seed layers and maintaining superior short-channel control, thus enhancing FinFET performance.
Implementation Method 1
a dielectric material laterally isolating the fin structure from the fin base edges
Implementation Method 2
improves source/drain epitaxy for better dopant incorporation and strain enhancement
Data Source
AI summary
A semiconductor structure is provided that includes a fin structure of, from bottom to top, a semiconductor punch through stop (PTS) doping fin portion, a dielectric material fin portion, and a topmost semiconductor fin portion that is present on a wider semiconductor fin base. A functional gate structure straddles the semiconductor fin structure. Portions of the wider semiconductor fin base that are not located directly beneath the fin structure of the present application and that are not covered by the functional gate structure can be used as an area for epitaxial growth of source/drain structures. The wide semiconductor fin base improves source/drain epitaxy for better dopant incorporation and strain enhancement.