Dielectric Isolation Structure for Mixed Transistor Regions on One Die
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Solution Overview
Problem
It is challenging to monolithically integrate different device types, such as vertical power MOSFETs and gate driver components, on the same semiconductor die due to structural and functional differences, which hinders efficiency improvements in circuit applications like buck converters.
Innovation Solution
The integration of a semiconductor device with an epitaxial layer or layer stack featuring transistor cells of different types, where an isolation structure with dielectric material laterally and vertically delimits the regions, allowing for the electrical isolation and parallel coupling of these cells, enabling the monolithic integration of diverse device types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If different device types (vertical power MOSFETs and lateral transistors) are monolithically integrated on the same semiconductor die, then circuit efficiency and switching frequency are improved, but manufacturing complexity and device isolation challenges increase
Solution Approach 1:
The semiconductor die is divided into distinct first and second regions, each dedicated to specific device types. Vertical power MOSFETs are confined to the first region while lateral transistors are placed in the second region, allowing each device type to be optimized independently while achieving monolithic integration.
Solution Approach 2:
An isolation structure comprising a dielectric material and positioned between the first and second regions serves as an intermediary element. This isolation structure electrically separates the vertical power MOSFETs from the lateral transistors, enabling independent device operation and preventing electrical interference while maintaining physical integration on the same die.
2Ease of operation
If vertical power MOSFETs and lateral transistors are placed in close proximity, then gate driver integration is improved, but electrical isolation between different device types becomes more difficult
Solution Approach 1:
The isolation structure with dielectric material acts as an intermediary barrier between the first region containing vertical power MOSFETs and the second region containing lateral transistors. This enables close proximity placement for improved gate driver integration while maintaining reliable electrical isolation through the dielectric barrier.
Solution Approach 2:
Different regions of the semiconductor die are assigned different functional qualities: the first region is optimized for vertical power MOSFETs with appropriate doping and structure, while the second region is optimized for lateral transistors. The isolation structure introduces localized dielectric quality at the region boundary to ensure electrical separation.
3Ease of manufacture
If a single epitaxial layer is used for both device types, then manufacturing simplicity is maintained, but electrical isolation between different transistor regions becomes challenging
Solution Approach 1:
The isolation structure comprising dielectric material serves as an intermediary element introduced during epitaxial processing. This allows a single continuous epitaxial layer to be used for both device types while the dielectric isolation structure provides the necessary electrical separation between different transistor regions.
Solution Approach 2:
The single epitaxial layer serves multiple functions: it provides the substrate for both vertical power MOSFETs in the first region and lateral transistors in the second region. The isolation structure enhances this universality by enabling different device types to coexist on the same epitaxial layer while maintaining electrical independence.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.