Dielectric Isolation Trenches for Multi-Die Semiconductor Packages
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Solution Overview
Problem
Existing methods for integrating multiple semiconductor dies in a package face challenges in achieving effective electrical isolation without wasting significant surface area or incurring costly manufacturing processes, such as the use of p-n junction structures or semiconductor on insulator techniques with trench isolation.
Innovation Solution
A semiconductor device with an isolation structure comprising an isolation trench filled with a dielectric material, where the trench traverses the thickness of the semiconductor die, allowing for efficient electrical isolation without occupying large surface area, and utilizing a combination of front-end and back-end etching processes to form the isolation structure, which can include filling with materials like silicon oxide or epoxy resin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-n junction structure is used for electrical isolation between dies, then current flow between adjacent dies is blocked, but significant surface area is wasted and diffusion process is time consuming
Solution Approach 1:
The patent transitions from surface-level isolation (p-n junctions requiring lateral diffusion width) to depth-based isolation (trenches extending vertically through the substrate). By etching isolation trenches from the front surface through the entire substrate thickness and filling them with dielectric material, electrical isolation is achieved without consuming significant surface area, as the isolation occurs in the vertical dimension rather than lateral dimension.
2Reliability
If p-n junction structure is used for electrical isolation, then current flow is blocked, but diffusion process is time consuming
Solution Approach 1:
The patent replaces the thermal diffusion process (time-consuming chemical process) with a mechanical etching process followed by dielectric filling. Instead of relying on slow dopant diffusion to create isolation, the method uses physical trench etching through the substrate and fills the trenches with insulating material, significantly reducing the time required to achieve electrical isolation.
3Reliability
If SOI technique with trench isolation is used, then each die is surrounded by oxide, but the process is complicated and involves burying oxide in substrate
Solution Approach 1:
The patent extracts the isolation function from the complex SOI process by implementing trenches only where die isolation is required, rather than surrounding each die with oxide on all sides. The isolation trenches are etched from the front surface through the substrate and filled with dielectric material, eliminating the need for complicated oxide burial processes while achieving sufficient electrical isolation between adjacent dies.
4Ease of manufacture
If conventional packaging with wirebonding is used, then dies can be packaged, but lengthy wirings are required in package or on PCB
Solution Approach 1:
The patent merges multiple semiconductor dies into a single integrated module by forming isolation trenches and interconnection structures within a common substrate. This integration eliminates the need for external wirebonds and lengthy PCB traces, as electrical connections between dies are established through direct substrate interconnections within the packaged module, significantly reducing overall wiring length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides sufficient electrical isolation without surface area wastage and avoids complex, costly manufacturing processes, enabling efficient packaging and integration of semiconductor dies as a module for flip chip form on PCBs.
Implementation Method 1
an isolation trench filled with a dielectric material, where the isolation structure traverses the thickness of the isolated semiconductor dies
Implementation Method 2
the isolation structure is formed by adopting a front-end etching process, in which the isolation trench is filled with a dielectric material
Data Source
AI summary
The disclosure provides a semiconductor package having an isolation structure comprising an isolation trench filled with dielectric material, where the isolation structure traverses the thickness of the isolated semiconductor dies.