Dielectric Isolation for CMOS Nanosheet Channel Devices
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Solution Overview
Problem
Current nanosheet FETs face challenges in reducing parasitic capacitance and short-channel effects due to close proximity of the gate and substrate, leading to increased RC delay and leakage currents, which conventional approaches have not adequately addressed.
Innovation Solution
The formation of a dielectric isolation layer between the gate and substrate using an epitaxially grown multilayer structure with varying germanium content SiGe layers, where a sacrificial SiGe(x+25) layer is selectively removed to create a nitride dielectric isolation region, reducing capacitive coupling and enhancing channel control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate is positioned close to the substrate to reduce device footprint, then device density is improved, but parasitic capacitance increases causing increased RC delay
Solution Approach 1:
A dielectric isolation layer is introduced as an intermediary between the gate and substrate. This intermediate layer increases the distance between gate and substrate, reducing parasitic capacitance and RC delay, while still allowing the gate to be positioned over the active region for compact device footprint.
2Reliability
If the gate is positioned close to the substrate to improve electrostatic control, then channel control is enhanced, but leakage currents increase due to short-channel effects
Solution Approach 1:
The dielectric isolation layer serves as a mediator that electrically isolates the gate from the substrate. This isolation reduces parasitic capacitance that causes short-channel effects and leakage currents, while the gate remains positioned to provide effective electrostatic control over the channel.
3Loss of energy
If a thick dielectric layer is formed between gate and substrate to reduce parasitic capacitance, then RC delay is reduced, but device footprint increases
Solution Approach 1:
Instead of increasing the lateral area to accommodate thick dielectric, the solution extends in the vertical dimension by forming a thick dielectric isolation layer between the gate and substrate. This vertical stacking approach reduces RC delay without increasing the device footprint.
4Ease of manufacture
If conventional isolation approaches are used to address parasitic capacitance, then manufacturing simplicity is maintained, but short-channel effects are not adequately mitigated
Solution Approach 1:
The channel region is segmented into multiple nanosheet layers stacked vertically. This segmentation allows the gate to wrap around and control each nanosheet segment, improving electrostatic control and reducing short-channel effects. The approach integrates with conventional fabrication processes while addressing reliability concerns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and mitigates short-channel effects, improving device performance by increasing the dielectric thickness between the gate and substrate, thereby enhancing electrostatic control and reducing leakage currents.
Implementation Method 1
The SiGe(x+25) layers are selectively removed to form a space between the SiGe(x) layers and a space between the substrate and a lowermost one of the SiGe(x) layers
Implementation Method 2
the substrate heated to diffuse the germanium in the SiGe(x) layer into the silicon layer to form a germanium diffused silicon layer
Implementation Method 3
An oxide layer is conformally deposited on the substrate, wherein the oxide layer is at a thickness effective to fill the space between the SiGe(x) layers
Data Source
AI summary
Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.