Self-Aligned Dielectric Isolation for Source/Drain Via Shorting
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Solution Overview
Problem
As the semiconductor industry advances beyond the 5 nm technology node, there is a challenge in preventing shorting of source/drains to adjacent metal vias or contacts in densely packed semiconductor devices, which limits cell scaling and device density.
Innovation Solution
A method is developed to form a conformal, self-aligned dielectric material as a spacer on the exposed surfaces of source/drains in vertically stacked gate-all-around field-effect transistors, using a low temperature plasma process to prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source/drains are densely packed to increase device density, then device density improves, but shorting between source/drains and metal vias/contacts occurs
Solution Approach 1:
A dielectric material is deposited as a spacer on the sidewalls of source/drain regions before metal via and contact formation. This preliminary dielectric layer prevents direct contact between metal elements and source/drains, eliminating shorting risks that would otherwise occur with dense packing.
Solution Approach 2:
The dielectric spacer acts as an intermediary barrier between conductive elements (source/drains and metal vias/contacts). This intermediate dielectric layer provides electrical isolation while allowing the structures to be positioned in close proximity, enabling high device density without compromising reliability.
2Reliability
If conventional isolation methods are used, then electrical isolation is achieved, but device scaling and density are limited
Solution Approach 1:
Instead of applying isolation uniformly across the entire device structure, the dielectric spacer is selectively formed only on the sidewalls of source/drain regions that require isolation from adjacent metal elements. This localized approach provides necessary electrical isolation while minimizing the overall device footprint.
Solution Approach 2:
The isolation solution transitions from a planar approach to a three-dimensional approach by forming dielectric spacers on the vertical sidewalls of source/drain regions. This vertical/dimensional isolation allows horizontal scaling and denser packing without compromising electrical isolation, as the isolation occurs in the vertical dimension rather than consuming horizontal space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively isolates source/drains from metal vias and contacts, allowing for more densely packed semiconductor devices without shorting, thereby enhancing device density and scaling capabilities.
Implementation Method 1
performing a low temperature plasma process on the two vertically stacked gate-all-around field-effect transistors, wherein the low temperature plasma process forms a layer of a dielectric material as a spacer on the exposed surfaces of the top source/drain
Data Source
AI summary
A semiconductor structure that includes a semiconductor element, where a portion of the semiconductor element extends into a metal element of the semiconductor structure. The semiconductor structure includes a dielectric material on the portion of the semiconductor element extending into the metal element. The dielectric material on the portion of the semiconductor element is formed with a self-limiting plasma process. The semiconductor element can be a source/drain of a field-effect transistor. The portion of semiconductor element such as a source/drain covered by the dielectric material extends into the metal element, such as an adjacent via. The dielectric material electrically isolates the portion of the source/drain extending into the via from shorting to the via. The field-effect transistor may be at least one of two vertically stacked field-effect transistors. The ability to electrically insulate the portions of the source/drain extending into adjacent vias allows densely packed vertically stacked gate-all-around transistors.