Dielectric Layer Fills Voids and Isolates Contacts in LED Devices
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Solution Overview
Problem
Semiconductor light emitting devices face structural weaknesses due to voids that can lead to damage during mounting and operation, and existing technologies require a separate non-planar dielectric layer for electrical isolation between n- and p-contacts, which complicates manufacturing and can result in device shorts.
Innovation Solution
A dielectric layer is used to fill voids and electrically isolate n- and p-contacts, eliminating the need for a buried dielectric layer and providing structural support, which is achieved by depositing a dielectric material between the metal contacts and planarizing the surface to ensure proper contact formation and device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate non-planar dielectric layer is used for electrical isolation between n- and p-contacts, then electrical isolation is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines the electrical isolation function with the void-filling dielectric layer already present in the device structure. By ensuring this single dielectric layer provides both mechanical support (filling voids) and electrical isolation between n- and p-contacts, the invention eliminates the need for a separate non-planar dielectric layer, thereby reducing device complexity while maintaining reliable electrical isolation
Solution Approach 2:
The dielectric layer is designed to perform multiple functions simultaneously: it fills voids to provide structural support, electrically isolates the n- and p-contacts, and serves as a base for subsequent processing steps. This multi-functionality eliminates the need for additional specialized layers, simplifying the overall device structure
2Ease of manufacture
If voids are left empty in the semiconductor structure, then manufacturing is simpler, but structural integrity deteriorates making the device susceptible to damage
Solution Approach 1:
The patent changes the physical state and distribution of the dielectric material by depositing it in a manner that completely fills void spaces within the device structure. This parameter change in material distribution transforms empty voids into solidified regions, thereby enhancing structural integrity without adding complex manufacturing steps
3Reliability
If additional underfill materials and intermetal dielectric layers are used, then electrical isolation is improved, but manufacturing complexity and time increase
Solution Approach 1:
The invention merges the functions of underfill material and intermetal dielectric layer into a single dielectric layer that simultaneously fills voids and provides electrical isolation. This consolidation reduces the number of manufacturing steps, decreases processing time, and improves manufacturing yields while maintaining reliable electrical isolation between contacts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the structural integrity of the semiconductor device, reduces the risk of device shorts, and improves manufacturing yields by eliminating the need for additional underfill materials and intermetal dielectric layers, while simplifying the bonding process and enhancing thermal performance.
Implementation Method 1
A dielectric layer is used to fill voids and electrically isolate n- and p-contacts
Implementation Method 2
depositing a dielectric material between the metal contacts
Implementation Method 3
planarizing the surface to ensure proper contact formation
Data Source
AI summary
A semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is formed. A portion of the light emitting layer and the p-type region are removed to expose a portion of the n-type region. A first metal contact is formed on an exposed portion of the n-type region and a second metal contact is formed on a remaining portion of the p-type region. The first and second metal contacts are formed on a same side of the semiconductor structure. A dielectric material is disposed between the first and second metal contacts. The dielectric material is in direct contact with a portion of the semiconductor structure, a portion of the first metal contact, and a portion of the second metal contact. A surface of the device is then planarized by removing a portion of at least one of the first metal contact, the second metal contact, and the dielectric material.