Dielectric Layer Planarization for Semiconductor Light Emitting Devices

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Solution Overview

Problem

Semiconductor light emitting devices face issues with voids that weaken the structure and cause damage during mounting and operation, and existing technologies require a separate non-planar dielectric layer for electrical isolation between n- and p-contacts, which can lead to device shorts and manufacturing defects.

Innovation Solution

A dielectric layer is used to fill voids and electrically isolate n- and p-contacts, eliminating the need for a buried dielectric layer and providing structural support, which is achieved by depositing a dielectric material between the metal contacts and planarizing the surface to ensure proper contact exposure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate non-planar dielectric layer is used for electrical isolation between n- and p-contacts, then electrical isolation is achieved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical isolationVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the electrical isolation function with the void-filling dielectric layer. The same dielectric material that fills the voids between the semiconductor structure and substrate also provides electrical isolation between the n- and p-contacts, eliminating the need for a separate buried dielectric layer and reducing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dielectric layer serves multiple functions simultaneously: it fills voids to provide structural support, electrically isolates the n- and p-contacts, and enables planarization of the device surface. This multi-functionality reduces the number of separate components needed

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If voids are left in the semiconductor structure, then manufacturing is simpler, but structural integrity is weakened and damage occurs during mounting and operation

Engineering Contradiction:
Improveease of manufactureVSAvoidstructural integrity
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The dielectric material is deposited to fill voids before the mounting and operation stages. This preliminary filling action prevents structural weakness from manifesting during subsequent processing steps, ensuring the device can withstand mounting stresses and operational thermal cycling without damage

Inventive Principle:
Principle #10Preliminary action

3Strength

If additional underfill materials and thick metal contacts are used, then structural support is improved, but manufacturing complexity and defect risk increase

Engineering Contradiction:
Improvestructural supportVSAvoidmanufacturing complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent merges the structural support function (originally requiring underfill materials) and the electrical isolation function into a single dielectric layer. This eliminates the need for separate underfill materials and thick metal contacts, reducing manufacturing complexity while maintaining structural integrity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the structural integrity of the semiconductor device, reduces the risk of device shorts and manufacturing defects, and improves thermal performance by eliminating the need for additional underfill materials and thick metal contacts, while simplifying the bonding process.

Implementation Method 1

A dielectric layer is used to fill voids and electrically isolate n- and p-contacts, eliminating the need for a buried dielectric layer and providing structural support, which is achieved by depositing a dielectric material between the metal contacts

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 2

planarizing the surface to ensure proper contact exposure

Methodology Applied
Scientific EffectPlanarization:

Data Source

PatentEP2438625B8Method of forming a dielectric layer on a semiconductor light emitting device, and semiconductor light emitting device with a dielectric layer
Publication Date: 2018.08.29 LUMILEDS HLDG BV

AI summary

A semiconductor structure comprising a light emitting layer disposed between an n- type region and a p-type region is formed. A first metal contact is formed on a portion of the n-type region and a second metal contact is formed on a portion of the p-type region. The first and second metal contacts are formed on a same side of the semiconductor structure. A dielectric material is disposed between the first and second metal contacts. The dielectric material is in direct contact with a portion of the semiconductor structure, a portion of the first metal contact, and a portion of the second metal contact. A planar surface is formed including a surface of the first metal contact, a surface of the second metal contact, and a surface of the dielectric material