Dielectric Layer Expansion for Tight-Pitch Via Patterning
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Solution Overview
Problem
Conventional lithography techniques struggle to accurately and economically form small features and tight pitches in semiconductor processes, particularly for conductive vias connecting to gate electrodes, due to resolution limits.
Innovation Solution
A method involving dielectric layer expansion through dopant species implantation, such as silicon oxide, to shrink openings and vias, allowing for precise and cost-effective formation of small features and tight pitches without the need for complex techniques like double-patterning or high-resolution masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography techniques are used to pattern small features, then the manufacturing process is simple and well-established, but the resolution and manufacturing precision deteriorate due to resolution limits
Solution Approach 1:
The patent segments the patterning process into two distinct stages: first forming openings at a relaxed pitch using conventional lithography, then applying a layer expansion process to shrink the openings to the final tight pitch. This segmentation allows each stage to operate within its optimal capability range, resolving the contradiction between using simple conventional lithography and achieving high precision.
Solution Approach 2:
The patent performs preliminary patterning of openings at a first pitch before the layer expansion process. This preliminary action creates a precursor pattern that will be subsequently shrunk, allowing the use of relaxed lithography conditions initially while still achieving the final tight pitch requirement through the expansion process.
2Manufacturing precision
If conventional lithography is used for tight pitch patterning, then manufacturing costs are lower, but the manufacturing precision and feature accuracy worsen
Solution Approach 1:
The patent divides the manufacturing approach into two phases: a cost-effective conventional lithography phase for initial opening formation, and a precision-enhancing layer expansion phase for achieving tight pitch accuracy. This segmentation allows the process to benefit from both low cost and high precision at different stages.
Solution Approach 2:
The patent changes the physical parameters of the dielectric layer through dopant implantation, inducing expansion that shrinks the openings. This parameter change transforms the pattern dimensions without requiring high-resolution lithography, thereby achieving accurate tight pitch patterning at lower manufacturing costs.
3Manufacturing precision
If high-resolution masks or double-patterning techniques are used, then manufacturing precision improves, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent segments the patterning challenge into conventional lithography for initial pattern formation and layer expansion for precision enhancement, avoiding the need for multiple lithography steps or high-resolution masks. This reduces overall process complexity while maintaining high precision.
Solution Approach 2:
Instead of trying to directly pattern tight pitch features using high-resolution methods, the patent inverts the approach by first creating relaxed pitch openings and then using layer expansion to shrink them to the desired tight pitch. This inversion simplifies the lithography requirements while achieving the same precision outcome.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the formation of small features and tight pitches in semiconductor manufacturing with improved accuracy and reduced manufacturing costs by expanding the dielectric layer to shrink openings, enhancing manufacturing flexibility and reducing misalignment tolerances.
Implementation Method 1
performing an expansion process on the dielectric layer to shrink the first width of the opening in the dielectric layer
Data Source
AI summary
Small sized and closely pitched features can be formed by patterning a layer to have holes therein and then expanding the layer so that the holes shrink. If the expansion is sufficient to pinch off the respective holes, multiple holes can be formed from one larger hole. Holes smaller and of closer pitch than practical or possible may be obtained in this way. One process for expanding the layer includes implanting a dopant species having a larger average atomic spacing than does the material of the layer.