Dielectric-Lined Bit Line Structure to Prevent Landing Pad Disconnection
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Solution Overview
Problem
The semiconductor industry faces challenges in precise control of lithography at advanced technology process nodes, leading to issues such as disconnection of landing pads due to sharp corners of bit line structures during etching, affecting device performance and yield.
Innovation Solution
A semiconductor structure is designed with a dielectric liner surrounding a polysilicon layer, which is surrounded by bit line structures, to prevent storage leakage and protect data integrity, while using a manufacturing method that involves forming spacers and dielectric layers to create a stable structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lithography control is pursued at advanced technology process nodes to achieve greater device density, then device density is improved, but manufacturing precision deteriorates due to disconnection of landing pads
Solution Approach 1:
A dielectric liner is formed along the sidewall of the polysilicon layer before subsequent processing steps. This preliminary protective layer prevents etching damage to the polysilicon layer during bit line structure formation, ensuring landing pads remain connected and preventing manufacturing defects at advanced process nodes
Solution Approach 2:
The dielectric liner acts as an intermediary protective layer between the polysilicon layer and the etching process. It shields the polysilicon layer from direct etching exposure, preventing over-etching and landing pad disconnection while allowing the bit line structures to be formed with precise control
2Measurement precision
If bit line structures are formed with sharp corners to improve lithography patterning, then lithography control is improved, but harmful factors increase due to landing pad disconnection
Solution Approach 1:
The dielectric liner serves as a protective intermediary that prevents the etching process from damaging the polysilicon layer even when sharp-cornered bit line structures are formed. This intermediary layer absorbs the harmful effects of over-etching and prevents landing pad disconnection
Solution Approach 2:
The dielectric liner provides beforehand cushioning protection to the polysilicon layer against potential etching damage. By placing this protective layer in advance, the structure is cushioned against the harmful effects of sharp corner formation and etching variability, preventing landing pad disconnection
Data Source
AI summary
The present application provides a semiconductor structure having dielectric liner and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a first bit line structure, disposed over the substrate, comprising a first conductive layer, a second conductive layer disposed over the first conductive layer, and a first dielectric layer disposed over the second conductive layer; a second bit line structure, disposed over the substrate, comprising a second dielectric layer, a third conductive layer disposed over the second dielectric layer, and a third dielectric layer disposed over the third conductive layer; a polysilicon layer, disposed over the substrate and surrounded by the first bit line structure and the second bit line structure; a dielectric liner, surrounding at least a portion of the polysilicon layer; and a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure.