Wrap-Around Dielectric Liner for Nanosheet Gate Isolation
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Solution Overview
Problem
As CMOS scaling continues, there is a challenge with shorting between backside contacts and transistor gates in nanosheet field effect transistors (FETs).
Innovation Solution
A wrap-around dielectric liner is used to prevent direct backside contacts from shorting to gates. This liner has horizontal portions that contact the top of the direct backside contact and vertical portions that contact the sidewalls of the direct backside contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If backside power rails and backside power distribution networks are used for CMOS scaling, then power distribution efficiency is improved, but shorting between backside contacts and transistor gates occurs
Solution Approach 1:
A dielectric liner is introduced as an intermediary layer between the backside contact and the gate. This liner acts as a physical barrier that prevents direct contact and potential shorting between the backside power distribution network and the transistor gate, while still allowing the backside power rails to function effectively for power distribution.
Solution Approach 2:
The dielectric liner extends into the vertical dimension by wrapping around the backside contact from the horizontal plane down into the trench. This three-dimensional configuration ensures that the liner provides comprehensive isolation not only at the surface level but also at deeper levels where the backside contact interfaces with the gate structure.
2Productivity
If CMOS scaling is continued to improve device density, then transistor density is improved, but shorting between backside contacts and gates becomes more likely
Solution Approach 1:
The dielectric liner serves as a protective intermediary that becomes increasingly important as devices are scaled down. In smaller feature sizes, the relative proximity between backside contacts and gates increases, making the liner's isolation function critical for preventing shorting while maintaining high device density.
Solution Approach 2:
The dielectric liner is nested within the trench structure, conformally coating the backside contact and extending down into the trench. This nested configuration provides robust isolation that scales effectively with device dimensions, ensuring reliable separation even as feature sizes decrease.
3Reliability
If a wrap-around dielectric liner is added to prevent shorting, then reliability is improved, but device complexity increases
Solution Approach 1:
The dielectric liner performs multiple functions simultaneously: it provides electrical isolation to prevent shorting, serves as a structural element defining the trench boundaries, and acts as a barrier to contaminant ingress. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The formation of the dielectric liner is combined with the existing trench isolation process. The liner is deposited conformally during the same processing sequence used to create the trench structure, merging two functions (isolation and structural definition) into a single integrated process step.
Data Source
AI summary
A wrap-around dielectric structure prevents backside contacts shorting to gates in nanosheet field effect transistors (FETs). A method of making same includes providing a sacrificial layer under a nanosheet stack adjacent shallow trench isolation (STI) regions, recessing the STI regions' liner to from gaps in communication with the sacrificial layer, removing the sacrificial layer to form a cavity, and filling the cavity and gaps with a continuous dielectric material which wraps around a subsequently formed backside contact.