Double Dielectric Liner for Memory Bit Layer Etch Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of memory arrays based on bulk resistance changes faces challenges such as sidewall damage and contamination during the etching process, leading to tapered profiles and degraded electrical characteristics of memory cells.
Innovation Solution
A dielectric liner structure is used to protect the memory bit layer from lateral erosion and contamination by depositing dielectric layers on the sidewalls of the memory bit layer before further etching through metal layers, minimizing exposure and maintaining the integrity of the memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etching is performed through metal layers to fabricate memory arrays, then the memory cell structure is formed, but lateral erosion and contamination damage the memory bit layer sidewalls
Solution Approach 1:
A dielectric liner layer is deposited between the memory bit layer and the etching environment, serving as a protective intermediary that prevents direct contact between the etchant and the memory bit layer sidewalls, thereby eliminating lateral erosion and contamination while allowing the etching process to proceed
Solution Approach 2:
The dielectric liner is deposited on the memory bit layer sidewalls before the etching process through metal layers is performed, providing pre-protection against the harmful effects of etching. This preliminary action ensures the memory bit layer maintains its intended thickness and shape throughout the fabrication process
2Ease of manufacture
If the memory bit layer is exposed during etching of metal layers, then the metal interconnect structure is formed, but the memory bit layer suffers lateral etching and tapered profile
Solution Approach 1:
The dielectric liner acts as a protective intermediary layer that allows the etching process to proceed through metal layers while preventing the etchant from attacking the memory bit layer, thus maintaining a vertical sidewall profile and preventing tapered shapes
Solution Approach 2:
The dielectric liner provides preliminary counter-protection against the lateral etching effect by being deposited on the memory bit layer sidewalls before the metal layer etching process, creating a barrier that opposes and prevents the harmful lateral erosion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces lateral etching and contamination, improving the electrical characteristics and performance of memory cells by maintaining the memory bit layer's thickness and structure during the etching process.
Implementation Method 1
depositing a dielectric layer over one or more sidewalls of at least the memory bit layer
Data Source
AI summary
A memory cell design is disclosed. In an embodiment, the memory cell structure includes at least one memory bit layer stacked between top and bottom electrodes. The memory bit layer provides a storage element for a corresponding memory cell. One or more additional conductive layers may be included between the memory bit layer and either, or both, of the top or bottom electrodes to provide a better ohmic contact. In any case, a dielectric liner structure is provided on sidewalls of the memory bit layer. The liner structure includes a dielectric layer, and may also include a second dielectric layer on a first dielectric layer. Either or both first dielectric layer or second dielectric layer comprises a high-k dielectric material. As will be appreciated, the dielectric liner structure effectively protects the memory bit layer from lateral erosion and contamination during the etching of subsequent layers beneath the memory bit layer.