Self-Assembled Dielectric Liners for Reliable Metal RIE Interconnects
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) scale down, the increased density and reduced spacing between elements lead to fabrication complexities, registration errors, and higher electric fields, resulting in increased capacitance, power consumption, and time delay, compromising reliability and increasing the risk of time-dependent dielectric breakdown (TDDB) failures.
Innovation Solution
Implementing self-assembled dielectric liners on conductive features to protect them during metal reactive-ion etching and mitigate registration errors, using materials with different etching rates to minimize capacitance and electric field strength, thereby reducing the risk of TDDB.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If spacing between conductive features is reduced to increase density, then element density increases, but fabrication complexity and registration errors increase
Solution Approach 1:
A dielectric liner is deposited on the conductive features before the metal RIE process. This preliminary protective layer prevents direct exposure of the conductive features to etchants, thereby reducing fabrication complexity and registration errors that would otherwise occur during subsequent etching processes.
Solution Approach 2:
The dielectric liner acts as an intermediary layer between the conductive features and the etchant environment. It mediates the interaction by providing a protective barrier that allows the RIE process to proceed without directly exposing the conductive features to harmful etchants, thus reducing fabrication complexity.
2Quantity of substance
If spacing between conductive features is reduced to increase density, then element density increases, but registration errors increase
Solution Approach 1:
The dielectric liner is applied in advance to the conductive features before the RIE process. This preliminary protective coating ensures that even if registration errors occur during subsequent processing steps, the conductive features are protected from direct etchant exposure, thereby maintaining manufacturing precision.
Solution Approach 2:
The dielectric liner provides beforehand cushioning protection to the conductive features. It acts as a buffer that absorbs or mitigates the impact of potential registration errors during the RIE process, preventing direct damage to the conductive features and thus improving manufacturing precision.
3Reliability
If operating voltage does not scale with feature sizes, then device functionality is maintained, but electric field strength increases
Solution Approach 1:
The dielectric liner serves as an intermediary layer that modifies the electric field distribution around the conductive features. By introducing this additional dielectric layer, the electric field strength is reduced while maintaining the necessary voltage levels for device operation, thus protecting device functionality.
Solution Approach 2:
The structure utilizes composite materials by combining the conductive features with the dielectric liner. This composite structure allows for optimized electrical properties, where the dielectric liner helps manage the electric field strength while the conductive features maintain the necessary voltage levels for device operation.
4Quantity of substance
If capacitance increases due to scaling, then device density increases, but power consumption increases
Solution Approach 1:
The dielectric liner acts as an intermediary that modifies the capacitive coupling between adjacent conductive features. By introducing this additional dielectric layer, the overall capacitance is reduced, which in turn reduces the power consumption associated with charging and discharging these capacitive elements, while still maintaining high device density.
5Quantity of substance
If capacitance increases due to scaling, then device density increases, but time delay increases
Solution Approach 1:
The dielectric liner serves as an intermediary that reduces the capacitive coupling between conductive features. By lowering the capacitance through this additional dielectric layer, the RC time constants are reduced, thereby decreasing the time delay associated with signal propagation while maintaining high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-assembled dielectric liners effectively protect conductive features from etchants and registration errors, reducing capacitance and electric field strength, thus enhancing the reliability and reducing the risk of TDDB failures in ICs.
Implementation Method 1
self-assembled dielectric liners on conductive features to protect them during metal reactive-ion etching
Implementation Method 2
using materials with different etching rates to minimize capacitance and electric field strength
Data Source
AI summary
Some embodiments of the present disclosure relate to a semiconductor structure including a first conductive wire disposed over a substrate and laterally surrounded by a first dielectric layer. A conductive via is disposed within a second dielectric layer over the first conductive wire. The conductive via has a first lower surface disposed over the first dielectric layer and a second lower surface below the first lower surface and over the first conductive wire.