Dielectric Lining Layers for CMOS Leakage Control
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Solution Overview
Problem
Miniaturization of solid-state transistors leads to increased parasitic capacitance and current leakage due to shorter gate lengths, necessitating improved reduction methods without compromising performance.
Innovation Solution
The use of dielectric lining layers with localized charges of defined polarity in CMOS transistors, eliminating the need for gate underlaps and electrode extensions, which attract mobile carriers to improve mobility and reduce leakage while maintaining high drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to increase performance and layout density, then productivity and layout density are improved, but parasitic capacitance and current leakage increase
Solution Approach 1:
The patent applies local quality by introducing dielectric lining layers with specifically engineered localized charges at critical interfaces (gate-to-drain and gate-to-source regions). These lining layers have distinct charge polarities tailored to repel specific carrier types, creating localized electrical properties that counteract short channel effects and reduce leakage current in miniaturized transistors while maintaining high layout density.
2Speed
If gate length is reduced to increase performance, then speed and performance are improved, but gate-induced drain leakage increases
Solution Approach 1:
The patent implements preliminary anti-action by pre-configuring dielectric lining layers with localized charges of appropriate polarity before transistor operation. These pre-established charged layers create repulsive forces against mobile carriers at gate-drain and gate-source interfaces, proactively preventing gate-induced drain leakage (GIDL) and other leakage mechanisms before they can occur during device operation, thereby enabling high-speed performance with reduced leakage.
3Object-generated harmful factors
If electrode extensions and gate underlaps are used to reduce leakage, then current leakage is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts and eliminates the need for complex electrode extensions and gate underlap structures by introducing a simpler alternative: dielectric lining layers with localized charges. This approach removes unnecessary structural complexity while effectively addressing leakage issues through electrical field control via the charged lining layers, thereby simplifying device architecture and manufacturing processes.
4Reliability
If doping is used to improve carrier mobility, then electrical conductivity is improved, but manufacturing precision and process complexity increase
Solution Approach 1:
The patent replaces the mechanical/chemical doping process with an electrical field control mechanism using dielectric lining layers containing localized charges. Instead of introducing dopant atoms to modify carrier mobility, the charged lining layers create electrical fields that attract or repel carriers, achieving mobility control through electrostatic effects rather than chemical doping, thereby eliminating doping precision challenges and process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates gate-induced drain-leakage and improves performance by attracting mobile carriers, reducing leakage while maintaining current drive, even with low energy bandgap channel materials, without relying on doping or electrode tips.
Implementation Method 1
dielectric lining layers with localized charges of defined polarity... attract mobile carriers to improve mobility and reduce leakage
Data Source
AI summary
Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.