Dual Damascene Interconnects via Dielectric Mask Pattern Transfer
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Solution Overview
Problem
Conventional dual damascene processes for forming interconnects in semiconductor devices face challenges in achieving precise pattern formation due to stress differences between low-k films and metal masks, leading to dimensional variations and pattern inaccuracies as feature sizes decrease.
Innovation Solution
A method where a first pattern is formed in both a metal film and an underlying dielectric layer, with the metal film being removed and the pattern transferred to the insulator layer using the dielectric layer as a mask, allowing for self-aligned via and trench formation without the metal mask, thereby reducing stress-induced inaccuracies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal mask is used to form fine patterns for self-aligned vias, then self-alignment precision is improved, but stress differences between the low-k film and metal mask cause strain at interfaces leading to pattern dimensional inaccuracies
Solution Approach 1:
The patent removes the metal mask from the process entirely. Instead of using a metal mask for self-alignment, the method forms patterns directly in the low-k interconnect dielectric film using photoresist masks and selective etching, eliminating the source of stress-induced dimensional errors while maintaining self-alignment through process design
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary mask between the photoresist pattern and the low-k film. This dielectric mask transfers the pattern without introducing stress, as it is stress-compatible with the low-k dielectric material, thereby achieving both self-alignment and dimensional accuracy
2Volume of moving object
If the line width of interconnects is decreased to enable miniaturization, then device density is improved, but reliability of damascene interconnects becomes more difficult to guarantee
Solution Approach 1:
The patent changes the etching parameters and process conditions to optimize for fine-line patterning. By adjusting etch selectivity, depth control, and profile formation parameters, the method achieves reliable trench and via formation at reduced dimensions while maintaining interconnect integrity
Solution Approach 2:
The patent performs preliminary pattern formation and self-alignment steps before trench etching. By pre-defining the exact locations and dimensions of vias and trenches through stress-free masking and pattern transfer, the method ensures reliable interconnect formation at smaller dimensions
Data Source
AI summary
An improved method of forming a semiconductor device including an interconnect layer formed using multilayer hard mask comprising metal mask and dielectric mask is provided. To form the second opening pattern being aligned to the first pattern, after the multilayer hard mask is used at the first step, then the dielectric mask is used to form a damascene structure in an insulator layer at the second step followed by removing the metal mask.