Dielectric Mesa Isolation for Silicon-on-Insulator Cost Reduction
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Solution Overview
Problem
The high cost of silicon-on-insulator wafers and difficulties in forming buried oxide layers with precise dimension control and reduced wafer stress, as well as challenges in forming thin device quality silicon layers over buried oxide layers, hinder the development of integrated circuits with dielectric isolation.
Innovation Solution
The formation of an isolation mesa of dielectric material over a single crystal substrate, followed by a selective epitaxial process to create a first epitaxial silicon-based layer, a non-selective epitaxial process to form a second epitaxial layer with a single-crystalline region on the first layer and a non-crystalline region on the mesa, and a radiantly-induced recrystallization process to convert the non-crystalline region into single-crystalline material, achieving a smooth and defect-reduced epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-on-insulator wafers are used to form integrated circuits with dielectric isolation, then isolation quality is improved, but wafer cost increases
Solution Approach 1:
The patent replaces expensive silicon-on-insulator wafers with a cost-effective alternative process using standard silicon wafers and forming dielectric isolation mesas through selective epitaxy and oxidation. This substitutes expensive reusable SOI wafers with cheaper process-formed structures that achieve the same isolation function.
Solution Approach 2:
The patent changes the fundamental approach from using pre-formed SOI wafers to creating isolation structures through controlled epitaxial growth and thermal oxidation processes. By changing parameters such as epitaxial growth conditions and oxidation temperature, the patent achieves dielectric isolation with standard wafers, eliminating the need for expensive SOI substrates.
2Reliability
If oxygen implantation is used to form buried oxide layers, then dielectric isolation is achieved, but lateral and vertical dimension control deteriorates
Solution Approach 1:
The patent replaces the oxygen implantation process (ion bombardment) with a chemical vapor deposition-based selective epitaxial growth process followed by thermal oxidation. This substitution of physical implantation with chemical growth processes provides superior control over layer thickness and lateral dimensions through well-established semiconductor manufacturing techniques.
Solution Approach 2:
The patent changes from fixed-parameter oxygen implantation to controllable epitaxial growth parameters including temperature, pressure, gas flow rates, and growth time. These parameters can be precisely adjusted to achieve desired oxide layer thickness and lateral extent, providing superior dimension control compared to implantation methods.
3Reliability
If oxygen implantation is used to form buried oxide layers, then dielectric isolation is achieved, but wafer stress increases
Solution Approach 1:
The patent replaces the high-stress oxygen implantation process with a low-stress selective epitaxial growth and thermal oxidation process. The chemical vapor deposition and thermal oxidation methods introduce minimal mechanical stress to the wafer, avoiding the damage and stress associated with ion implantation while still achieving effective dielectric isolation.
4Reliability
If thin layers of device quality silicon are formed over buried oxide layers, then device quality is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent employs selective epitaxial growth that automatically forms high-quality silicon layers only in regions where the substrate is exposed, self-limiting the growth to achieve uniform thin layers with excellent crystal quality. The process uses the substrate topography itself to control where material is deposited, eliminating the need for complex external control mechanisms.
Solution Approach 2:
The patent changes from difficult post-growth thinning processes to controlled in-situ epitaxial growth that directly forms the desired thin layer thickness during the growth process itself. By controlling temperature, pressure, and growth time, the patent achieves precise thickness control of device-quality silicon layers without subsequent mechanical or chemical thinning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the cost-effective formation of integrated circuits with precise control over epitaxial layer thickness and reduced stress, enabling efficient dielectric isolation while minimizing defects and achieving a planarized, high-quality single-crystalline semiconductor layer.
Implementation Method 1
performing a selective epitaxial process which forms a first epitaxial layer of silicon-based semiconductor material on the substrate adjacent to the isolation mesa
Implementation Method 2
A non-selective epitaxial process forms a second epitaxial layer of silicon-based semiconductor material on the first epitaxial layer and isolation mesa
Implementation Method 3
a radiantly-induced recrystallization process causes the non-crystalline material to form single-crystalline semiconductor over the isolation mesa
Data Source
AI summary
An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.