Dielectric Metal Liner for Fin Erosion Prevention

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Solution Overview

Problem

Semiconductor fins are prone to erosion during manufacturing processes, leading to poorly defined source and drain regions and degraded device performance in fin field effect transistors due to anisotropic etch processes.

Innovation Solution

A dielectric metal compound liner is deposited on semiconductor fins to protect them during the formation of gate spacers, which can be removed before forming source and drain regions, ensuring the fins are safeguarded throughout the processing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If anisotropic etch processes are employed to form gate spacers, then gate spacers can be formed, but semiconductor fins are heavily eroded and insulator layers are severely gouged

Engineering Contradiction:
Improvegate spacer formationVSAvoidfin definition
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A mandrel structure is introduced as an intermediary element between the etch process and the semiconductor fin. The mandrel serves as a protective template that enables gate spacer formation through self-aligned deposition while preventing direct contact between the etch chemistry and the fin surface, thus avoiding erosion and maintaining fin definition.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mandrel structure is formed in advance before the gate spacer formation process. This preliminary structure provides a self-aligned template that guides subsequent material deposition, ensuring precise gate spacer placement without requiring additional alignment steps or exposing the fin to harmful etching.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If anisotropic etch processes are used to form gate spacers, then gate spacers are formed, but insulator layers between fins are severely gouged

Engineering Contradiction:
Improvegate spacer formationVSAvoidinsulator layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The mandrel structure acts as a protective intermediary that prevents etch chemistry from contacting the insulator layer. By forming gate spacers through self-aligned deposition on the mandrel rather than through direct etching of the insulator, the integrity of the insulator layer is preserved while still achieving gate spacer formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If semiconductor fins are exposed during gate spacer formation, then gate spacers can be formed, but source and drain regions become poorly defined

Engineering Contradiction:
Improvegate spacer formationVSAvoidsource and drain region definition
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The mandrel structure is formed preliminarily to provide a self-aligned template for gate spacer deposition. This preliminary structure ensures that the gate spacer forms with precise alignment, which in turn defines the source and drain regions accurately by establishing clear lateral boundaries, preventing poor definition that would result from fin exposure.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dielectric metal compound liner effectively minimizes erosion of semiconductor fins, maintaining their integrity and improving the definition of source and drain regions, thereby enhancing the performance of fin field effect transistors.

Implementation Method 1

A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS8809920B2Prevention of fin erosion for semiconductor devices
Publication Date: 2014.08.19 GLOBALFOUNDRIES US INC
  • US8809920B2 patent drawing
  • US8809920B2 patent drawing
  • US8809920B2 patent drawing

AI summary

A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.