Protective Dielectric Overlap for Bond Pad Crack Mitigation
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Solution Overview
Problem
Dielectric layers in microelectronic devices are prone to cracking in areas of high stress, particularly over underlying topography such as bond pads, leading to potential failure of the microelectronic device.
Innovation Solution
Increasing the overlap of the protective dielectric layer over the bond pads and decreasing the bond pad sidewall angle to less than seventy-five degrees reduces the maximum stress and shifts the location of maximum stress away from the dielectric layer corners, thereby minimizing cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the protective dielectric layer is increased in overlap over the bond pads, then the hermetic seal is improved, but the dielectric stress concentration at corners is worsened
Solution Approach 1:
The patent applies parameter changes by modifying the bond pad sidewall angle from a near-vertical profile to a trapezoidal profile with an angle of less than seventy-five degrees. This geometric parameter change reduces the stress concentration factor at the dielectric layer corners while preserving the hermetic seal function through adequate overlap.
Solution Approach 2:
The patent utilizes curvature by transitioning from a vertical (sharp corner) sidewall profile to a trapezoidal profile with sloped sides. This curvature modification at the bond pad corners reduces the stress singularity in the overlying dielectric layer, preventing crack initiation while maintaining the seal integrity.
2Strength
If the bond pad sidewall angle is decreased to reduce stress, then dielectric layer cracking is reduced, but the manufacturing precision requirement is worsened
Solution Approach 1:
The patent specifies a quantitative parameter range for the sidewall angle (less than seventy-five degrees) that balances stress reduction with manufacturing feasibility. This parameter optimization allows standard fabrication processes to achieve the desired trapezoidal profile while obtaining sufficient stress mitigation to prevent dielectric cracking.
3Reliability
If the protective dielectric layer overlap is increased to ensure hermetic seal, then device reliability is improved, but the device complexity is worsened
Solution Approach 1:
The patent optimizes the overlap dimension to a specific range (at least twice the dielectric layer thickness) that provides sufficient hermetic seal without excessive material usage or structural complexity. This parameter optimization achieves reliability while maintaining manufacturability.
Data Source
AI summary
A microelectronic device may have a protective dielectric layer over the top metal layer of the microelectronic device which provides a portion of a hermetic seal between the microelectronic device and the environment. The protective dielectric layer may also improve resistance to physical damage of the microelectronic device before packaging. The protective dielectric layer may have bond pad openings to allow electrical contact between the microelectronic device to a microelectronic package. The protective dielectric layer may overlap the bond pads to ensure the hermetic seal of the microelectronic device. Cracking of the protective dielectric layer in the region where the protective dielectric layer overlaps the bond pad may lead to failure of the microelectronic device. Stress analysis using finite element methods (FEM) and experimental data show that increasing the overlap of the protective dielectric layer over the bond pad may reduce protective dielectric layer cracking.