Overlay Mark Structure Using Dielectric Openings for Error Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in accurately measuring overlay errors between current and pre-layers due to systematic errors, particularly in lithography operations, which affect the precision of pattern alignment.
Innovation Solution
A semiconductor device and method that incorporates a new overlay mark structure comprising metallization layers as a pre-layer and openings defined by a dielectric layer as the current layer, allowing for precise measurement of overlay errors without systematic errors, using geometric centers to determine X- and Y-directional deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional overlay mark structures are used for measuring overlay errors, then the measurement process is simple, but systematic errors occur between current layer and pre-layer that reduce measurement precision
Solution Approach 1:
The overlay mark structure is divided into separate current layer patterns and pre-layer patterns with distinct geometric configurations. The current layer contains patterns oriented in one direction while the pre-layer contains patterns oriented in a perpendicular direction, allowing independent characterization and elimination of systematic errors through differential measurement
Solution Approach 2:
A dielectric layer with defined openings serves as an intermediary structure between the current layer metallization and the pre-layer metallization. This intermediary enables precise alignment reference and facilitates the measurement of overlay errors without direct contact between the metallization layers, thereby eliminating systematic errors
2Measurement precision
If new overlay mark structure with dielectric layer openings is used, then systematic errors are eliminated improving measurement accuracy, but the structure and manufacturing process become more complex
Solution Approach 1:
The dielectric layer with openings is formed and patterned before the metallization layers are deposited. This preliminary structuring establishes precise alignment references in advance, allowing subsequent lithography and deposition processes to align to these pre-defined geometric centers, thereby simplifying the overall manufacturing workflow despite the additional initial steps
Solution Approach 2:
The patent utilizes changes in material properties and layer configurations - specifically using dielectric material with defined opening geometries rather than continuous structures, and controlling the dimensional parameters of openings to be larger than the metallization features. This parameter change enables the openings to serve as robust alignment references that are insensitive to minor manufacturing variations
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a first pattern and a second pattern. The first pattern is disposed on the substrate. The first pattern includes a first segment and a second segment, each of which extends along a first direction. The second pattern is disposed on the first pattern. The second pattern includes a first part extending along a second direction different from the first direction. The first part of the second pattern overlaps the first segment and the second segment along a third direction different from the first direction and the second direction. The first pattern and the second pattern are associated with an overlay error.