Dielectric Layer Patterning With Cyclic Etch and Hard Mask Protection
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Solution Overview
Problem
Current semiconductor processing technologies face challenges in achieving precise control of sidewall profiles and pattern transfer fidelity for nanoscale features with high aspect ratios, particularly in advanced IC designs, due to limitations in plasma etch technology and hard mask material loss during etching.
Innovation Solution
The method involves a cyclic etch process combined with area selective deposition (ASD) techniques, where a capping layer or reconstructed hard mask layer is formed over the patterned hard mask to protect the dielectric layer during etching, allowing for precise control of etch rates and minimizing hard mask material loss, and a concurrent deposition and etch process that selectively coats the hard mask layer while removing material from the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etch technology is used for nanoscale patterning, then etching speed is maintained, but sidewall profile control and pattern transfer fidelity deteriorate for high aspect ratio features
Solution Approach 1:
The etching process is divided into multiple cycles, each consisting of a deposition step followed by an etching step. This segmentation allows the process to achieve both precise sidewall control and efficient material removal by repeating short etching intervals with protective deposition intervals.
Solution Approach 2:
A capping layer is introduced as an intermediary material deposited over the hard mask layer. This capping layer acts as a protective mediator that prevents hard mask material loss during etching, thereby improving sidewall profile control while allowing faster etching of the dielectric layer.
2Length of stationary object
If longer etch time is used to remove deep dielectric material, then etching depth is achieved, but hard mask material loss increases
Solution Approach 1:
The capping layer is deposited in advance before the etching step. This preliminary protective action ensures that the hard mask layer is shielded from etchant exposure, preventing material loss even during extended etching periods required for deep dielectric removal.
Solution Approach 2:
The process employs periodic cycles of deposition and etching. During each cycle, the capping layer is periodically replenished to maintain protection of the hard mask layer, enabling sustained deep etching without cumulative hard mask material loss.
3Manufacturing precision
If multiple patterning steps are implemented to achieve smaller features, then manufacturing precision is improved, but process complexity and manufacturing time increase
Solution Approach 1:
The cyclic etch process maintains continuous useful action by combining deposition and etching in a single integrated process flow. This continuity achieves precise pattern transfer in one process sequence rather than requiring multiple separate patterning steps, thereby reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of sidewall profile control and improves pattern transfer fidelity, enabling the formation of high aspect ratio features with reduced defects and increased manufacturing yield.
Implementation Method 1
forming a capping layer selectively over the patterned hard mask layer
Implementation Method 2
performing a timed etch process, the timed etch process removing material from the dielectric layer
Implementation Method 3
performing a concurrent deposition and etch process to remove a portion of the dielectric layer, the concurrent deposition and etch process including removing material from the dielectric layer, and selectively coating the patterned hard mask layer with hard mask material
Data Source
AI summary
A method is described for patterning a dielectric layer disposed over a semiconductor substrate layer. The patterning process includes forming a patterned hard mask layer over the dielectric layer, the patterned hard mask layer exposing a portion of a major surface of the dielectric layer. A portion of the dielectric layer is removed by a cyclic etch process, where performing one cycle of the cyclic etch process comprises forming a capping layer selectively over the patterned hard mask layer and performing a timed etch process that removes material from the dielectric layer. In another method, the deposition over the hard mask and the removal of the portion of the dielectric layer are performed concurrently.