Semiconductor Dielectric Patterning With Directional Etching for Tight Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink, the spacing between elements (pitch) becomes less than what can be manufactured using traditional optical masks and photolithography equipment, leading to challenges in achieving the desired device dimensions and increasing process complexity.
Innovation Solution
The use of a directional etching process, which involves directing ions at a shallow angle to etch sidewalls of photoresist layers and mask layers, allowing for the expansion of patterned openings and reduction of separation distances between conductive features, thereby enabling the formation of denser metal lines within semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional optical masks and photolithography equipment are used, then manufacturing process is simple, but pitch between elements cannot be reduced below certain limit
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages: first forming initial patterns using photolithography, then using directional etching to further subdivide and refine features. This multi-stage approach enables pitch reduction beyond single-step photolithography limits while managing process complexity through systematic breakdown of operations.
Solution Approach 2:
The patent introduces a new dimension to the patterning process by employing directional etching at shallow angles, adding a lateral etching component to the traditional vertical etching approach. This dimensional change enables precise control over feature geometry and pitch without requiring proportionally higher photolithography resolution.
2Manufacturing precision
If photolithography equipment is used, then process steps are limited, but desired pitch cannot be achieved
Solution Approach 1:
The patent introduces directional etching as an intermediary process between photolithography and final pattern formation. This intermediate step translates the limitations of photolithography into opportunities for precision etching, achieving desired pitch by mediating between the coarse photolithography pattern and the fine final structure through controlled lateral etching.
3Manufacturing precision
If additional patterning steps are used, then pitch can be reduced, but process time and cost increase
Solution Approach 1:
The patent merges the patterning and etching functions into a more integrated process flow. By combining photolithography with immediate directional etching in a coordinated sequence, the process achieves pitch reduction without requiring fully separate patterning cycles, thereby reducing total process time while maintaining precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the reduction of end-to-end separation distances between conductive lines, increasing pattern density and reducing semiconductor device size, while also improving process efficiency and reducing costs by minimizing the need for additional patterning steps.
Implementation Method 1
The use of a directional etching process, which involves directing ions at a shallow angle to etch sidewalls of photoresist layers and mask layers
Data Source
AI summary
A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.