Dielectric Layer Planarization Using an Obtuse-Angle Sidewall

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Solution Overview

Problem

Existing methods for planarizing semiconductor device surfaces, particularly in the context of magnetoresistive random-access memory (MRAM), often result in surface damage such as dents or scratches, leading to potential short circuits due to metal bridging between wires during metal interconnection processes, affecting device performance and yield.

Innovation Solution

A method involving the formation of a sidewall structure with an obtuse angle between the etched side surface and top surface of a protruding dielectric layer portion, followed by controlled etching and polishing to planarize the dielectric layer, enhancing the strength and feasibility of the planarization process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If conventional planarization methods are used on dielectric layers covering protruding MRAM structures, then the surface can be flattened, but the surface of the dielectric layer is damaged with dents or scratches that cause metal bridging and short circuits

Engineering Contradiction:

Improveflatness of dielectric layer surfaceVSAvoidintegrity of dielectric layer surface

Core Design Contradiction:

ShapeVSReliability

Solution Approach 1:

A protective coating layer is formed on the dielectric layer before the planarization process. This preliminary protective layer prevents direct contact between the polishing medium and the dielectric layer surface, thereby avoiding dents and scratches while still allowing the underlying surface to be planarized through the protective layer

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The protective coating layer acts as a cushioning layer that absorbs the mechanical stress and friction during polishing. This cushioning effect protects the dielectric layer surface from direct damage while enabling the planarization process to proceed without causing surface defects

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Manufacturing precision

If the dielectric layer is planarized to ensure a flat surface for subsequent metal interconnection, then manufacturing precision is improved, but surface damage occurs leading to short circuits

Engineering Contradiction:

Improveflatness of dielectric layerVSAvoidsurface damage causing short circuits

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The protective coating layer serves as an intermediary between the polishing medium and the dielectric layer. It mediates the planarization process by providing a sacrificial layer that can be polished without damaging the underlying dielectric layer, thus achieving the required surface flatness while preventing harmful surface defects

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If the surface of the dielectric layer is planarized by direct polishing, then the process is simple and fast, but dents or scratches are formed on the surface

Engineering Contradiction:

Improveplanarization process efficiencyVSAvoidsurface quality of dielectric layer

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The protective coating layer is applied beforehand to enable a more aggressive and efficient polishing process. The presence of this sacrificial layer allows for faster material removal rates without compromising the quality of the underlying dielectric layer surface, thus improving productivity while maintaining manufacturing precision

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method prevents surface damage during polishing, improves polishing efficiency, and enhances the yield and performance of semiconductor devices by ensuring the sidewall structure maintains integrity during planarization.

Implementation Method 1

A portion of the protruding portion is etched to form a sidewall structure

Methodology Applied

Scientific EffectEtching:

Implementation Method 2

The sidewall structure is removed to planarize the dielectric layer

Methodology Applied

Scientific EffectPolishing: Abrasion

Data Source

PatentUS20250372397A1Method for planarizing surface of semiconductor device

Publication Date: 2025.12.04 UNITED MICROELECTRONICS CORP

AI summary

A method for planarizing a surface of a semiconductor device includes steps as follows. A substrate defining a memory region is provided. A memory component is disposed on the substrate and located in the memory region. A dielectric layer is formed to cover the memory component. The dielectric layer includes a protruding portion corresponding to the memory component. A portion of the protruding portion is etched to form a sidewall structure. The sidewall structure includes an etched side surface, and an included angle between the etched side surface of the sidewall structure and an etched top surface of the protruding portion is an obtuse angle. The sidewall structure is removed to planarize the dielectric layer.