Dielectric Plug for Flash Memory Contact Alignment

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Solution Overview

Problem

In flash memory devices, particularly in NAND and NOR architectures, the reduced spacing between memory cells increases the likelihood of misaligned contacts between data lines and drain select gates, leading to electrical shorts between adjacent columns of memory cells, which is a challenge in maintaining memory density and reliability.

Innovation Solution

The introduction of a dielectric plug over an isolation region between active regions in the source/drain zones, which has a lower etch rate than the isolation regions, reduces the likelihood of shorts by preventing the etchant from reaching the adjacent active region during processing errors, ensuring accurate contact formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If spacing between memory cells is reduced to increase density, then memory density is improved, but contact alignment precision deteriorates leading to electrical shorts

Engineering Contradiction:
Improvememory densityVSAvoidcontact alignment precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

A dielectric plug is introduced as an intermediary structure between adjacent active regions. This plug serves as a protective barrier that prevents etchant from reaching and damaging adjacent active regions during contact formation processes, thereby compensating for the reduced alignment precision caused by decreased spacing between memory cells.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric plug is formed in advance before contact holes are etched. This preliminary protective structure cushions against potential misalignment issues by providing a buffer zone that prevents etchant from causing shorts between adjacent columns, allowing the process to tolerate greater variation in contact alignment.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Quantity of substance

If spacing between memory cells is reduced to increase density, then memory density is improved, but reliability deteriorates due to increased likelihood of electrical shorts

Engineering Contradiction:
Improvememory densityVSAvoiddevice reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The dielectric plug acts as an intermediary protective layer between adjacent active regions. During contact hole etching, this plug prevents the etchant from creating unintended conductive paths between adjacent columns, thereby maintaining device reliability even when spacing is reduced to increase density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional etching process is used without protective structures, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to contact misalignment

Engineering Contradiction:
Improveprocess complexityVSAvoidcontact alignment precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The dielectric plug is formed as a preliminary protective structure before the contact hole etching process. This advance preparation ensures that even if alignment is not perfect during subsequent steps, the etchant will not cause shorts because the plug provides a protective barrier that compensates for the misalignment.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively minimizes the occurrence of electrical shorts between misaligned contacts and adjacent active regions, enhancing the reliability and density of flash memory devices by maintaining precise contact alignment and reducing processing errors.

Implementation Method 1

a dielectric plug over an isolation region between active regions in the source/drain zones, which has a lower etch rate than the isolation regions

Methodology Applied
Scientific EffectEtch rate difference:

Data Source

PatentUS9530683B2Forming source/drain zones with a dielectric plug over an isolation region between active regions
Publication Date: 2016.12.27 MICRON TECHNOLOGY INC
  • US9530683B2 patent drawing
  • US9530683B2 patent drawing
  • US9530683B2 patent drawing

AI summary

An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.