Dielectric Plug and Polymer Island Layout for Package Crack Relief
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Solution Overview
Problem
The stress applied by the top polymer layer in semiconductor packaging can lead to cracking of underlying dielectric layers, compromising the reliability of the package.
Innovation Solution
Patterning the top polymer layer to form discrete polymer islands or forming openings in the top polymer layer, which reduces the stress applied to underlying dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous top polymer layer is used to cover redistribution lines, then complete coverage and protection are achieved, but stress concentration occurs leading to cracking of underlying dielectric layers
Solution Approach 1:
The continuous polymer layer is segmented into discrete polymer islands that are spaced apart from each other. Each polymer island covers a specific redistribution line or interconnect structure, while the spacing between islands allows stress to be distributed and prevents crack propagation across the entire structure. This segmentation maintains protective coverage where needed while eliminating the stress concentration problem of a continuous layer.
2Object-affected harmful factors
If openings are formed in the top polymer layer, then stress on underlying dielectric layers is reduced, but exposure of underlying structures increases
Solution Approach 1:
The polymer layer is configured with non-uniform local properties: discrete polymer islands provide coverage and protection specifically over the redistribution lines and interconnect structures that need protection, while the spaced regions provide stress relief. This local quality approach ensures that protection is applied only where necessary rather than uniformly across the entire structure, thereby reducing stress exposure of underlying dielectric layers while maintaining protection of critical conductive elements.
Data Source
AI summary
A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.


