Dielectric Protection Layer for Trimmed Multi-Wafer Interconnects
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Solution Overview
Problem
The edge trimming process in multi-dimensional integrated chip fabrication causes damage to inter-level dielectric (ILD) layers, leading to cracks and reduced yield due to thermomechanical stresses during subsequent fabrication processes.
Innovation Solution
A dielectric protection layer is formed over the sidewalls of the ILD layers after the edge trimming process to prevent further damage from mechanical, thermal, and thermomechanical stresses, using materials like silicon nitride or silicon dioxide with a thickness sufficient to protect the ILD layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If edge trimming process is performed to remove parts along perimeter, then mechanical strength is improved, but ILD layers are damaged causing cracks
Solution Approach 1:
A dielectric protection layer is formed over the ILD layers before the edge trimming process. This preliminary protective action prevents the trimming blade from directly contacting and damaging the ILD layers, allowing the edge trimming to proceed while maintaining ILD layer integrity.
Solution Approach 2:
The dielectric protection layer acts as an intermediary between the edge trimming blade and the ILD layers. This intermediate layer absorbs the mechanical stress and prevents direct transmission of damaging forces to the ILD layers, resolving the contradiction between achieving clean edges and protecting underlying structures.
2Productivity
If subsequent fabrication processes are performed, then manufacturing progress is achieved, but thermomechanical stresses cause cracks in ILD layers
Solution Approach 1:
The dielectric protection layer is formed in advance before subsequent fabrication processes. This preliminary protective measure ensures that when thermomechanical stresses occur during later processing steps, the ILD layers are already shielded and cannot be damaged by these stress conditions.
Solution Approach 2:
The dielectric protection layer provides beforehand cushioning against thermomechanical stresses. By being in place before the stressful fabrication processes, it creates a buffer that absorbs and distributes thermal and mechanical stresses, preventing crack formation in the ILD layers during normal manufacturing operations.
3Device complexity
If no protection layer is used, then device complexity is reduced, but yield is reduced due to damage
Solution Approach 1:
The introduction of the dielectric protection layer changes the structural parameters of the device by adding an additional layer. While this increases device complexity, it is a minimal structural addition that provides substantial protection and significantly improves yield by preventing damage during edge trimming and subsequent processing.
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method may be performed by forming a plurality of interconnect layers within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an interior sidewall disposed directly over the first semiconductor substrate. A dielectric protection layer is formed onto a sidewall of the first interconnect structure after performing the edge trimming process.